2a50921553
This patch utilizes the -maix-small-local-exec-tls option to produce a faster, non-TOC-based access sequence for the local-exec TLS model. Specifically, for when the offsets from the TLS variable are non-zero. In particular, this patch produces either a single: - addi/la with a displacement off of R13 plus a non-zero offset for when an address is calculated, or - load or store off of R13 plus a non-zero offset for when an address is calculated and used for further access where R13 is the thread pointer, respectively. In order to produce a single addi or load/store off of the thread pointer with a non-zero offset, this patch also adds the necessary support in the assembly printer when printing these instructions. Specifically: - The non-zero offset is added to the TLS variable address when the address of the TLS variable + it's offset is less than 32KB. - Otherwise, when the address of the TLS variable + its offset is greater than 32KB, the non-zero offset (and a multiple of 64KB) is subtracted from the TLS address. This handling in the assembly printer is necessary to ensure that the TLS address + the non-zero offset is between [-32768, 32768), so that the total displacement can fit within the addi/load/store instructions. This patch is meant to be a follow-up to 3f46e5453d9310b15d974e876f6132e3cf50c4b1 (where the optimization occurs for when the offset is zero).
178 lines
7.8 KiB
LLVM
178 lines
7.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
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; RUN: -mtriple powerpc64-ibm-aix-xcoff -mattr=+aix-small-local-exec-tls < %s \
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; RUN: | FileCheck %s --check-prefix=SMALL-LOCAL-EXEC-SMALLCM64
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-asm-full-reg-names \
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; RUN: -mtriple powerpc64-ibm-aix-xcoff --code-model=large \
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; RUN: -mattr=+aix-small-local-exec-tls < %s | FileCheck %s \
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; RUN: --check-prefix=SMALL-LOCAL-EXEC-LARGECM64
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@ThreadLocalVarInit = thread_local(localexec) global double 1.000000e+00, align 8
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@VarInit = local_unnamed_addr global double 8.700000e+01, align 8
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@IThreadLocalVarInit = internal thread_local(localexec) global double 1.000000e+00, align 8
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declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #1
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@f = thread_local(localexec) global [87 x double] zeroinitializer, align 8
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define nonnull ptr @AddrTest1() local_unnamed_addr #0 {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: AddrTest1:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: la r3, f[TL]@le+48(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: AddrTest1:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: la r3, f[TL]@le+48(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @f)
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%arrayidx = getelementptr inbounds [87 x double], ptr %0, i64 0, i64 6
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ret ptr %arrayidx
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}
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define void @storeITLInit(double noundef %x) {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: storeITLInit:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: stfd f1, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: storeITLInit:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: stfd f1, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
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store double %x, ptr %0, align 8
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ret void
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}
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define void @storeTLInit(double noundef %x) {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: storeTLInit:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: stfd f1, ThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: storeTLInit:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: stfd f1, ThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
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store double %x, ptr %0, align 8
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ret void
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}
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define double @loadITLInit() {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: loadITLInit:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: lfd f1, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: loadITLInit:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: lfd f1, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
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%1 = load double, ptr %0, align 8
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ret double %1
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}
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define double @loadITLInit2() {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: loadITLInit2:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: ld r3, L..C0(r2) # @VarInit
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: lfd f0, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: lfd f1, 0(r3)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: xsadddp f1, f0, f1
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: loadITLInit2:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: addis r3, L..C0@u(r2)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: lfd f0, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: ld r3, L..C0@l(r3)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: lfd f1, 0(r3)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: xsadddp f1, f0, f1
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
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%1 = load double, ptr %0, align 8
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%2 = load double, ptr @VarInit, align 8
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%add = fadd double %1, %2
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ret double %add
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}
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define double @loadTLInit() {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: loadTLInit:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: lfd f1, ThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: loadTLInit:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: lfd f1, ThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
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%1 = load double, ptr %0, align 8
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ret double %1
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}
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define double @loadTLInit2() {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: loadTLInit2:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: ld r3, L..C0(r2) # @VarInit
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: lfd f0, ThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: lfd f1, 0(r3)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: xsadddp f1, f0, f1
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: loadTLInit2:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: addis r3, L..C0@u(r2)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: lfd f0, ThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: ld r3, L..C0@l(r3)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: lfd f1, 0(r3)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: xsadddp f1, f0, f1
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
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%1 = load double, ptr %0, align 8
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%2 = load double, ptr @VarInit, align 8
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%add = fadd double %1, %2
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ret double %add
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}
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define void @loadStore1(double noundef %x) {
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; SMALL-LOCAL-EXEC-SMALLCM64-LABEL: loadStore1:
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; SMALL-LOCAL-EXEC-SMALLCM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: vspltisw v2, 1
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: lfd f1, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: xvcvsxwdp vs0, vs34
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: vspltisw v3, 8
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: xsadddp f0, f1, f0
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: xvcvsxwdp vs1, vs35
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: xsadddp f0, f0, f1
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: stfd f0, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-SMALLCM64-NEXT: blr
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;
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; SMALL-LOCAL-EXEC-LARGECM64-LABEL: loadStore1:
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; SMALL-LOCAL-EXEC-LARGECM64: # %bb.0: # %entry
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: vspltisw v2, 1
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: lfd f1, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: xvcvsxwdp vs0, vs34
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: vspltisw v3, 8
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: xsadddp f0, f1, f0
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: xvcvsxwdp vs1, vs35
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: xsadddp f0, f0, f1
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: stfd f0, IThreadLocalVarInit[TL]@le(r13)
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; SMALL-LOCAL-EXEC-LARGECM64-NEXT: blr
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entry:
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%0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarInit)
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%1 = load double, ptr %0, align 8
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%inc = fadd double %1, 1.000000e+00
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%add = fadd double %inc, 8.000000e+00
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store double %add, ptr %0, align 8
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ret void
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}
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