85a9f2e148
In PowerPC, the AtomicCmpXchgInst is lowered to ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS. However, this node does not handle the weak attribute of AtomicCmpXchgInst. As a result, when compiling C++ atomic_compare_exchange_weak_explicit, the generated assembly includes a "reservation lost" loop — i.e., it branches back and retries if the stwcx. (store-conditional) fails. This differs from GCC’s codegen, which does not include that loop for weak compare-exchange. Since PowerPC uses LL/SC-style atomic instructions, the patch enables AtomicExpandImpl::expandAtomicCmpXchg for PowerPC. With this, the weak attribute is properly respected, and the "reservation lost" loop is removed for weak operations. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
115 lines
3.1 KiB
LLVM
115 lines
3.1 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=ppc64-- | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
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; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
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; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr7 | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -ppc-asm-full-reg-names -mtriple=ppc64-- -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U
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define i64 @exchange_and_add(ptr %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange_and_add:
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; CHECK: ldarx
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%tmp = atomicrmw add ptr %mem, i64 %val monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i8 @exchange_and_add8(ptr %mem, i8 %val) nounwind {
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; CHECK-LABEL: exchange_and_add8:
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; CHECK-BE: xori
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; CHECK-LE-NOT: xori
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; CHECK-P8U: lbarx
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%tmp = atomicrmw add ptr %mem, i8 %val monotonic
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; CHECK-P8U: stbcx.
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ret i8 %tmp
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}
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define i16 @exchange_and_add16(ptr %mem, i16 %val) nounwind {
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; CHECK-LABEL: exchange_and_add16:
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; CHECK-BE: xori
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; CHECK-LE-NOT: xori
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; CHECK-P8U: lharx
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%tmp = atomicrmw add ptr %mem, i16 %val monotonic
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; CHECK-P8U: sthcx.
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ret i16 %tmp
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}
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define i64 @exchange_and_cmp(ptr %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp:
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; CHECK: ldarx
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%tmppair = cmpxchg ptr %mem, i64 0, i64 1 monotonic monotonic
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%tmp = extractvalue { i64, i1 } %tmppair, 0
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i8 @exchange_and_cmp8(ptr %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp8:
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; CHECK-BE: or r{{.*}} r{{.*}} r{{.*}}
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; CHECK-LE-NOT: or r{{.*}} r{{.*}} r{{.*}}
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; CHECK-P8U: lbarx
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%tmppair = cmpxchg ptr %mem, i8 0, i8 1 monotonic monotonic
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%tmp = extractvalue { i8, i1 } %tmppair, 0
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; CHECK-P8U: stbcx.
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ret i8 %tmp
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}
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define i16 @exchange_and_cmp16(ptr %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp16:
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; CHECK-BE: xori
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; CHECK-LE-NOT: xori
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; CHECK-P8U: lharx
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%tmppair = cmpxchg ptr %mem, i16 0, i16 1 monotonic monotonic
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%tmp = extractvalue { i16, i1 } %tmppair, 0
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; CHECK-P8U: sthcx.
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ret i16 %tmp
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}
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define i64 @exchange(ptr %mem, i64 %val) nounwind {
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; CHECK-LABEL: exchange:
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; CHECK: ldarx
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%tmp = atomicrmw xchg ptr %mem, i64 1 monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i8 @exchange8(ptr %mem, i8 %val) nounwind {
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; CHECK-LABEL: exchange8:
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; CHECK-BE: xori
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; CHECK-LE-NOT: xori
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; CHECK-P8U: lbarx
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%tmp = atomicrmw xchg ptr %mem, i8 1 monotonic
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; CHECK-P8U: stbcx.
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ret i8 %tmp
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}
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define i16 @exchange16(ptr %mem, i16 %val) nounwind {
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; CHECK-LABEL: exchange16:
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; CHECK-BE: xori
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; CHECK-LE-NOT: xori
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; CHECK-P8U: lharx
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%tmp = atomicrmw xchg ptr %mem, i16 1 monotonic
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; CHECK-P8U: sthcx.
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ret i16 %tmp
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}
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define void @atomic_store(ptr %mem, i64 %val) nounwind {
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entry:
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; CHECK: @atomic_store
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store atomic i64 %val, ptr %mem release, align 64
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; CHECK: lwsync
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; CHECK-NOT: stdcx
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; CHECK: std
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ret void
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}
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define i64 @atomic_load(ptr %mem) nounwind {
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entry:
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; CHECK: @atomic_load
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%tmp = load atomic i64, ptr %mem acquire, align 64
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; CHECK-NOT: ldarx
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; CHECK: ld [[VAL:r[0-9]+]]
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; CHECK: cmpd [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
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; CHECK: bne- [[CR]], .+4
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; CHECK: isync
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ret i64 %tmp
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}
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