a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
169 lines
5.3 KiB
LLVM
169 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
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; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
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; This is already checked for in Atomics-64.ll
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; RUN: llc < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
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; In this file, we check that atomic load/store can make use of the indexed
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; versions of the instructions.
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; Indexed version of loads
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define i8 @load_x_i8_seq_cst(ptr %mem) {
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; PPC32-LABEL: load_x_i8_seq_cst:
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; PPC32: # %bb.0:
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; PPC32-NEXT: lis r4, 1
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; PPC32-NEXT: sync
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; PPC32-NEXT: ori r4, r4, 24464
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; PPC32-NEXT: lbzx r3, r3, r4
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; PPC32-NEXT: cmpw cr7, r3, r3
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; PPC32-NEXT: bne- cr7, .+4
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; PPC32-NEXT: isync
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_x_i8_seq_cst:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 1
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; PPC64-NEXT: sync
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; PPC64-NEXT: ori r4, r4, 24464
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; PPC64-NEXT: lbzx r3, r3, r4
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; PPC64-NEXT: cmpd cr7, r3, r3
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; PPC64-NEXT: bne- cr7, .+4
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; PPC64-NEXT: isync
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; PPC64-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i8], ptr %mem, i64 0, i64 90000
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%val = load atomic i8, ptr %ptr seq_cst, align 1
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ret i8 %val
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}
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define i16 @load_x_i16_acquire(ptr %mem) {
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; PPC32-LABEL: load_x_i16_acquire:
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; PPC32: # %bb.0:
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; PPC32-NEXT: lis r4, 2
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; PPC32-NEXT: ori r4, r4, 48928
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; PPC32-NEXT: lhzx r3, r3, r4
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; PPC32-NEXT: cmpw cr7, r3, r3
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; PPC32-NEXT: bne- cr7, .+4
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; PPC32-NEXT: isync
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_x_i16_acquire:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 2
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; PPC64-NEXT: ori r4, r4, 48928
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; PPC64-NEXT: lhzx r3, r3, r4
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; PPC64-NEXT: cmpd cr7, r3, r3
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; PPC64-NEXT: bne- cr7, .+4
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; PPC64-NEXT: isync
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; PPC64-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i16], ptr %mem, i64 0, i64 90000
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%val = load atomic i16, ptr %ptr acquire, align 2
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ret i16 %val
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}
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define i32 @load_x_i32_monotonic(ptr %mem) {
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; CHECK-LABEL: load_x_i32_monotonic:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 5
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; CHECK-NEXT: ori r4, r4, 32320
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; CHECK-NEXT: lwzx r3, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 90000
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%val = load atomic i32, ptr %ptr monotonic, align 4
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ret i32 %val
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}
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define i64 @load_x_i64_unordered(ptr %mem) {
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; PPC32-LABEL: load_x_i64_unordered:
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; PPC32: # %bb.0:
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; PPC32-NEXT: mflr r0
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; PPC32-NEXT: stwu r1, -16(r1)
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; PPC32-NEXT: stw r0, 20(r1)
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; PPC32-NEXT: .cfi_def_cfa_offset 16
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; PPC32-NEXT: .cfi_offset lr, 4
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; PPC32-NEXT: addi r3, r3, -896
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; PPC32-NEXT: addis r3, r3, 11
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; PPC32-NEXT: li r4, 0
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; PPC32-NEXT: bl __atomic_load_8
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; PPC32-NEXT: lwz r0, 20(r1)
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; PPC32-NEXT: addi r1, r1, 16
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; PPC32-NEXT: mtlr r0
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: load_x_i64_unordered:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 10
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; PPC64-NEXT: ori r4, r4, 64640
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; PPC64-NEXT: ldx r3, r3, r4
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; PPC64-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i64], ptr %mem, i64 0, i64 90000
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%val = load atomic i64, ptr %ptr unordered, align 8
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ret i64 %val
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}
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; Indexed version of stores
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define void @store_x_i8_seq_cst(ptr %mem) {
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; CHECK-LABEL: store_x_i8_seq_cst:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 1
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; CHECK-NEXT: ori r4, r4, 24464
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; CHECK-NEXT: li r5, 42
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; CHECK-NEXT: sync
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; CHECK-NEXT: stbx r5, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i8], ptr %mem, i64 0, i64 90000
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store atomic i8 42, ptr %ptr seq_cst, align 1
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ret void
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}
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define void @store_x_i16_release(ptr %mem) {
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; CHECK-LABEL: store_x_i16_release:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 2
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; CHECK-NEXT: ori r4, r4, 48928
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; CHECK-NEXT: li r5, 42
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: sthx r5, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i16], ptr %mem, i64 0, i64 90000
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store atomic i16 42, ptr %ptr release, align 2
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ret void
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}
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define void @store_x_i32_monotonic(ptr %mem) {
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; CHECK-LABEL: store_x_i32_monotonic:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lis r4, 5
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; CHECK-NEXT: ori r4, r4, 32320
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; CHECK-NEXT: li r5, 42
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; CHECK-NEXT: stwx r5, r3, r4
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; CHECK-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i32], ptr %mem, i64 0, i64 90000
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store atomic i32 42, ptr %ptr monotonic, align 4
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ret void
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}
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define void @store_x_i64_unordered(ptr %mem) {
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; PPC32-LABEL: store_x_i64_unordered:
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; PPC32: # %bb.0:
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; PPC32-NEXT: mflr r0
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; PPC32-NEXT: stwu r1, -16(r1)
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; PPC32-NEXT: stw r0, 20(r1)
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; PPC32-NEXT: .cfi_def_cfa_offset 16
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; PPC32-NEXT: .cfi_offset lr, 4
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; PPC32-NEXT: addi r3, r3, -896
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; PPC32-NEXT: addis r3, r3, 11
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; PPC32-NEXT: li r5, 0
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; PPC32-NEXT: li r6, 42
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; PPC32-NEXT: li r7, 0
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; PPC32-NEXT: bl __atomic_store_8
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; PPC32-NEXT: lwz r0, 20(r1)
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; PPC32-NEXT: addi r1, r1, 16
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; PPC32-NEXT: mtlr r0
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; PPC32-NEXT: blr
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;
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; PPC64-LABEL: store_x_i64_unordered:
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; PPC64: # %bb.0:
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; PPC64-NEXT: lis r4, 10
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; PPC64-NEXT: ori r4, r4, 64640
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; PPC64-NEXT: li r5, 42
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; PPC64-NEXT: stdx r5, r3, r4
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; PPC64-NEXT: blr
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%ptr = getelementptr inbounds [100000 x i64], ptr %mem, i64 0, i64 90000
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store atomic i64 42, ptr %ptr unordered, align 8
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ret void
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}
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