b5e1fc19da
We added a new post-isel CTRLoop pass in D122125. That pass will expand the hardware loop related intrinsic to CTR loop or normal loop based on the loop context. So we don't need to conservatively check the CTR clobber now on the IR level. Reviewed By: lkail Differential Revision: https://reviews.llvm.org/D135847
84 lines
3.7 KiB
LLVM
84 lines
3.7 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "E-p:32:32"
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target triple = "powerpc-unknown-linux-gnu"
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;CHECK-LABEL: foo:
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; There are 4 inner loops (%bb, %bb12, %bb25, %bb38) that all exit to %cond_next48
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; The last (whichever it is) should have a fallthrough exit, and the other three
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; need an unconditional branch. No other block should have an unconditional
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; branch to cond_next48
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; One of the blocks ends up with a loop exit block that gets a tail-duplicated copy
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; of %cond_next48, so there should only be two unconditional branches.
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;CHECK: b .LBB0_13
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;CHECK: b .LBB0_13
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;CHECK-NOT: b .LBB0_13
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;CHECK: .LBB0_13: # %cond_next48
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define void @foo(i32 %W, i32 %X, i32 %Y, i32 %Z) {
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entry:
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%tmp1 = and i32 %W, 1 ; <i32> [#uses=1]
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%tmp1.upgrd.1 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp1.upgrd.1, label %cond_false, label %bb5
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bb: ; preds = %bb5, %bb
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%indvar77 = phi i32 [ %indvar.next78, %bb ], [ 0, %bb5 ] ; <i32> [#uses=1]
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%tmp2 = tail call i32 (...) @bar( ) ; <i32> [#uses=0]
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%indvar.next78 = add i32 %indvar77, 1 ; <i32> [#uses=2]
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%exitcond79 = icmp eq i32 %indvar.next78, %X ; <i1> [#uses=1]
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br i1 %exitcond79, label %cond_next48, label %bb
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bb5: ; preds = %entry
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%tmp = icmp eq i32 %X, 0 ; <i1> [#uses=1]
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br i1 %tmp, label %cond_next48, label %bb
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cond_false: ; preds = %entry
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%tmp10 = and i32 %W, 2 ; <i32> [#uses=1]
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%tmp10.upgrd.2 = icmp eq i32 %tmp10, 0 ; <i1> [#uses=1]
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br i1 %tmp10.upgrd.2, label %cond_false20, label %bb16
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bb12: ; preds = %bb16, %bb12
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%indvar72 = phi i32 [ %indvar.next73, %bb12 ], [ 0, %bb16 ] ; <i32> [#uses=1]
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%tmp13 = tail call i32 (...) @bar( ) ; <i32> [#uses=0]
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%indvar.next73 = add i32 %indvar72, 1 ; <i32> [#uses=2]
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%exitcond74 = icmp eq i32 %indvar.next73, %Y ; <i1> [#uses=1]
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br i1 %exitcond74, label %cond_next48, label %bb12
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bb16: ; preds = %cond_false
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%tmp18 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
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br i1 %tmp18, label %cond_next48, label %bb12
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cond_false20: ; preds = %cond_false
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%tmp23 = and i32 %W, 4 ; <i32> [#uses=1]
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%tmp23.upgrd.3 = icmp eq i32 %tmp23, 0 ; <i1> [#uses=1]
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br i1 %tmp23.upgrd.3, label %cond_false33, label %bb29
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bb25: ; preds = %bb29, %bb25
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%indvar67 = phi i32 [ %indvar.next68, %bb25 ], [ 0, %bb29 ] ; <i32> [#uses=1]
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%tmp26 = tail call i32 (...) @bar( ) ; <i32> [#uses=0]
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%indvar.next68 = add i32 %indvar67, 1 ; <i32> [#uses=2]
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%exitcond69 = icmp eq i32 %indvar.next68, %Z ; <i1> [#uses=1]
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br i1 %exitcond69, label %cond_next48, label %bb25
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bb29: ; preds = %cond_false20
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%tmp31 = icmp eq i32 %Z, 0 ; <i1> [#uses=1]
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br i1 %tmp31, label %cond_next48, label %bb25
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cond_false33: ; preds = %cond_false20
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%tmp36 = and i32 %W, 8 ; <i32> [#uses=1]
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%tmp36.upgrd.4 = icmp eq i32 %tmp36, 0 ; <i1> [#uses=1]
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br i1 %tmp36.upgrd.4, label %cond_next48, label %bb42
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bb38: ; preds = %bb42
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%tmp39 = tail call i32 (...) @bar( ) ; <i32> [#uses=0]
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
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br label %bb42
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bb42: ; preds = %bb38, %cond_false33
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%indvar = phi i32 [ %indvar.next, %bb38 ], [ 0, %cond_false33 ] ; <i32> [#uses=4]
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%W_addr.0 = sub i32 %W, %indvar ; <i32> [#uses=1]
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%exitcond = icmp eq i32 %indvar, %W ; <i1> [#uses=1]
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br i1 %exitcond, label %cond_next48, label %bb38
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cond_next48: ; preds = %bb42, %cond_false33, %bb29, %bb25, %bb16, %bb12, %bb5, %bb
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%W_addr.1 = phi i32 [ %W, %bb5 ], [ %W, %bb16 ], [ %W, %bb29 ], [ %W, %cond_false33 ], [ %W_addr.0, %bb42 ], [ %W, %bb25 ], [ %W, %bb12 ], [ %W, %bb ] ; <i32> [#uses=1]
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%tmp50 = icmp eq i32 %W_addr.1, 0 ; <i1> [#uses=1]
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br i1 %tmp50, label %UnifiedReturnBlock, label %cond_true51
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cond_true51: ; preds = %cond_next48
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%tmp52 = tail call i32 (...) @bar( ) ; <i32> [#uses=0]
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ret void
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UnifiedReturnBlock: ; preds = %cond_next48
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ret void
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}
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declare i32 @bar(...)
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