2377eca93c
The lowering for v2i64 is now guarded with hasDirectMove, however, the current lowering can handle the pattern correctly, only lowering it when there is efficient patterns and corresponding instructions. The original guard was added in D21135, and was for Legal action. The code has evloved now, this guard is not necessary anymore. Reviewed By: #powerpc, nemanjai Differential Revision: https://reviews.llvm.org/D105596
108 lines
2.8 KiB
LLVM
108 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
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; RUN: -check-prefix=P7BE
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; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
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; RUN: -check-prefix=P8LE
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
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; RUN: -check-prefix=P9LE
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; FIXME: P7BE for i128 looks wrong.
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define <1 x i128> @One1i128() {
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; P7BE-LABEL: One1i128:
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; P7BE: # %bb.0: # %entry
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; P7BE-NEXT: li r3, -1
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; P7BE-NEXT: li r4, -1
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; P7BE-NEXT: blr
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;
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; P8LE-LABEL: One1i128:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One1i128:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <1 x i128> <i128 -1>
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}
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define <2 x i64> @One2i64() {
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; P7BE-LABEL: One2i64:
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; P7BE: # %bb.0: # %entry
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; P7BE-NEXT: vspltisb v2, -1
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; P7BE-NEXT: blr
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;
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; P8LE-LABEL: One2i64:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One2i64:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <2 x i64> <i64 -1, i64 -1>
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}
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define <4 x i32> @One4i32() {
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; P7BE-LABEL: One4i32:
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; P7BE: # %bb.0: # %entry
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; P7BE-NEXT: vspltisb v2, -1
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; P7BE-NEXT: blr
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;
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; P8LE-LABEL: One4i32:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One4i32:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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}
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define <8 x i16> @One8i16() {
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; P7BE-LABEL: One8i16:
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; P7BE: # %bb.0: # %entry
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; P7BE-NEXT: vspltisb v2, -1
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; P7BE-NEXT: blr
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;
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; P8LE-LABEL: One8i16:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One8i16:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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}
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define <16 x i8> @One16i8() {
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; P7BE-LABEL: One16i8:
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; P7BE: # %bb.0: # %entry
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; P7BE-NEXT: vspltisb v2, -1
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; P7BE-NEXT: blr
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;
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; P8LE-LABEL: One16i8:
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; P8LE: # %bb.0: # %entry
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; P8LE-NEXT: xxleqv vs34, vs34, vs34
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; P8LE-NEXT: blr
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;
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; P9LE-LABEL: One16i8:
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; P9LE: # %bb.0: # %entry
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; P9LE-NEXT: xxleqv vs34, vs34, vs34
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; P9LE-NEXT: blr
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entry:
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ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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}
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