64510c1411
Implement BCD assist builtins for XL and GCC compatibility. GCC compat: ``` unsigned int __builtin_cdtbcd (unsigned int); unsigned int __builtin_cbcdtd (unsigned int); unsigned int __builtin_addg6s (unsigned int, unsigned int); ``` 64BIT XL compat: ``` long long __cdtbcd (long long); long long __cbcdtd (long long); long long __addg6s (long long source1, long long source2) ```
80 lines
2.3 KiB
LLVM
80 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux \
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; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
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define i64 @cdtbcd_test(i64 noundef %ll) {
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; CHECK-LABEL: cdtbcd_test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cdtbcd r3, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %ll)
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ret i64 %0
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}
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define zeroext i32 @cdtbcd_test_ui(i32 noundef zeroext %ui) {
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; CHECK-LABEL: cdtbcd_test_ui:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cdtbcd r3, r3
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%conv = zext i32 %ui to i64
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%0 = tail call i64 @llvm.ppc.cdtbcdd(i64 %conv)
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%conv1 = trunc i64 %0 to i32
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ret i32 %conv1
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}
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define i64 @cbcdtd_test(i64 noundef %ll) {
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; CHECK-LABEL: cbcdtd_test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cbcdtd r3, r3
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %ll)
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ret i64 %0
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}
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define zeroext i32 @cbcdtd_test_ui(i32 noundef zeroext %ui) {
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; CHECK-LABEL: cbcdtd_test_ui:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cbcdtd r3, r3
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%conv = zext i32 %ui to i64
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%0 = tail call i64 @llvm.ppc.cbcdtdd(i64 %conv)
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%conv1 = trunc i64 %0 to i32
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ret i32 %conv1
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}
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define i64 @addg6s_test(i64 noundef %ll, i64 noundef %ll2) {
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; CHECK-LABEL: addg6s_test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addg6s r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i64 @llvm.ppc.addg6sd(i64 %ll, i64 %ll2)
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ret i64 %0
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}
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define zeroext i32 @addg6s_test_ui(i32 noundef zeroext %ui, i32 noundef zeroext %ui2) {
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; CHECK-LABEL: addg6s_test_ui:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addg6s r3, r3, r4
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%conv = zext i32 %ui to i64
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%conv1 = zext i32 %ui2 to i64
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%0 = tail call i64 @llvm.ppc.addg6sd(i64 %conv, i64 %conv1)
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%conv2 = trunc i64 %0 to i32
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ret i32 %conv2
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}
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declare i64 @llvm.ppc.cdtbcdd(i64)
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declare i64 @llvm.ppc.cbcdtdd(i64)
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declare i64 @llvm.ppc.addg6sd(i64, i64)
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