427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
99 lines
2.9 KiB
LLVM
99 lines
2.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
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@us = external global i16, align 2
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@us_addr = external global ptr, align 8
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@ui = external global i32, align 4
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@ui_addr = external global ptr, align 8
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define dso_local void @test_builtin_ppc_store2r() {
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; CHECK-64B-LABEL: test_builtin_ppc_store2r:
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; CHECK-64B: sthbrx 3, 0, 4
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_store2r:
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; CHECK-32B: sthbrx 3, 0, 4
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load i16, ptr @us, align 2
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%conv = zext i16 %0 to i32
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%1 = load ptr, ptr @us_addr, align 8
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call void @llvm.ppc.store2r(i32 %conv, ptr %1)
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ret void
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}
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declare void @llvm.ppc.store2r(i32, ptr)
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define dso_local void @test_builtin_ppc_store4r() {
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; CHECK-64B-LABEL: test_builtin_ppc_store4r:
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; CHECK-64B: stwbrx 3, 0, 4
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_store4r:
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; CHECK-32B: stwbrx 3, 0, 4
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load i32, ptr @ui, align 4
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%1 = load ptr, ptr @ui_addr, align 8
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call void @llvm.ppc.store4r(i32 %0, ptr %1)
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ret void
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}
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declare void @llvm.ppc.store4r(i32, ptr)
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define dso_local zeroext i16 @test_builtin_ppc_load2r() {
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; CHECK-64B-LABEL: test_builtin_ppc_load2r:
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; CHECK-64B: lhbrx 3, 0, 3
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_load2r:
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; CHECK-32B: lhbrx 3, 0, 3
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load ptr, ptr @us_addr, align 8
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%1 = call i32 @llvm.ppc.load2r(ptr %0)
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%conv = trunc i32 %1 to i16
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ret i16 %conv
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}
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define dso_local signext i16 @test_builtin_ppc_load2r_signext() {
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; CHECK-64B-LABEL: test_builtin_ppc_load2r_signext:
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; CHECK-64B: lhbrx 3, 0, 3
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; CHECK-64B-NEXT: extsh 3, 3
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_load2r_signext:
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; CHECK-32B: lhbrx 3, 0, 3
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; CHECK-32B-NEXT: extsh 3, 3
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load ptr, ptr @us_addr, align 8
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%1 = call i32 @llvm.ppc.load2r(ptr %0)
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%conv = trunc i32 %1 to i16
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ret i16 %conv
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}
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declare i32 @llvm.ppc.load2r(ptr)
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define dso_local zeroext i32 @test_builtin_ppc_load4r() {
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; CHECK-64B-LABEL: test_builtin_ppc_load4r:
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; CHECK-64B: lwbrx 3, 0, 3
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_load4r:
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; CHECK-32B: lwbrx 3, 0, 3
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load ptr, ptr @ui_addr, align 8
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%1 = call i32 @llvm.ppc.load4r(ptr %0)
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ret i32 %1
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}
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declare i32 @llvm.ppc.load4r(ptr)
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