53c37f300d
On PowerPC there are 128 bit VSX registers. These registers are half overlapped with 64 bit floating point registers (FPR). The 64 bit half of the VXS register that does not overlap with the FPR does not overlap with any other register class. The FPR are the only subregisters of the VSX registers but they do not fully cover the 128 bit super register. This leads to incorrect lane masks being created. This patch adds phony registers for the other half of the VSX registers in order to fully cover them and to make sure that the lane masks are not the same for the VSX and the floating point register.
442 lines
15 KiB
LLVM
442 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefix=CHECK-P9
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define float @FloatConstantPool() {
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; CHECK-LABEL: FloatConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsplti32dx vs1, 0, 940572664
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; CHECK-NEXT: xxsplti32dx vs1, 1, 1073741824
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: FloatConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-P9-NEXT: lfs f1, .LCPI0_0@toc@l(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret float 0x380FFFF840000000
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}
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define double @DoubleConstantPool() {
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; CHECK-LABEL: DoubleConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsplti32dx vs1, 0, 1048574
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; CHECK-NEXT: xxsplti32dx vs1, 1, 780229072
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: DoubleConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-P9-NEXT: lfd f1, .LCPI1_0@toc@l(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret double 2.225070e-308
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}
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define ppc_fp128 @LongDoubleConstantPool() {
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; CHECK-LABEL: LongDoubleConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsplti32dx vs1, 0, 56623104
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; CHECK-NEXT: xxsplti32dx vs2, 0, -2146625897
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; CHECK-NEXT: xxsplti32dx vs1, 1, -609716532
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; CHECK-NEXT: xxsplti32dx vs2, 1, 1339675259
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: LongDoubleConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-P9-NEXT: lfd f1, .LCPI2_0@toc@l(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI2_1@toc@ha
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; CHECK-P9-NEXT: lfd f2, .LCPI2_1@toc@l(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret ppc_fp128 0xM03600000DBA876CC800D16974FD9D27B
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}
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define fp128 @__Float128ConstantPool() {
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; CHECK-LABEL: __Float128ConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI3_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: __Float128ConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret fp128 0xL00000000000000003C00FFFFC5D02B3A
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}
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define <16 x i8> @VectorCharConstantPool() {
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; CHECK-LABEL: VectorCharConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI4_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: VectorCharConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret <16 x i8> <i8 -128, i8 -127, i8 -126, i8 -125, i8 -124, i8 -123, i8 -122, i8 -121, i8 -120, i8 -119, i8 -118, i8 -117, i8 -116, i8 -115, i8 -114, i8 -113>
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}
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define <8 x i16> @VectorShortConstantPool() {
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; CHECK-LABEL: VectorShortConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI5_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: VectorShortConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret <8 x i16> <i16 -32768, i16 -32767, i16 -32766, i16 -32765, i16 -32764, i16 -32763, i16 -32762, i16 -32761>
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}
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define <4 x i32> @VectorIntConstantPool() {
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; CHECK-LABEL: VectorIntConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI6_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: VectorIntConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret <4 x i32> <i32 -2147483648, i32 -2147483647, i32 -2147483646, i32 -2147483645>
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}
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define <2 x i64> @VectorLongLongConstantPool() {
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; CHECK-LABEL: VectorLongLongConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI7_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: VectorLongLongConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI7_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI7_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret <2 x i64> <i64 -9223372036854775808, i64 -9223372036854775807>
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}
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define <1 x i128> @VectorInt128ConstantPool() {
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; CHECK-LABEL: VectorInt128ConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI8_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: VectorInt128ConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI8_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI8_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret <1 x i128> <i128 -27670116110564327424>
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}
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define <4 x float> @VectorFloatConstantPool() {
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; CHECK-LABEL: VectorFloatConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI9_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: VectorFloatConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret <4 x float> <float 0x380FFFF840000000, float 0x380FFF57C0000000, float 0x3843FFFB20000000, float 0x3843FF96C0000000>
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}
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define <2 x double> @VectorDoubleConstantPool() {
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; CHECK-LABEL: VectorDoubleConstantPool:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs34, .LCPI10_0@PCREL(0), 1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: VectorDoubleConstantPool:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l
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; CHECK-P9-NEXT: lxv vs34, 0(r3)
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; CHECK-P9-NEXT: blr
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entry:
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ret <2 x double> <double 2.225070e-308, double 2.225000e-308>
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}
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define double @two_constants(double %a) {
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; CHECK-LABEL: two_constants:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsplti32dx vs0, 0, 1074446467
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; CHECK-NEXT: xxsplti32dx vs0, 1, 309237645
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; CHECK-NEXT: xsadddp f0, f1, f0
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; CHECK-NEXT: xxsplti32dx vs1, 0, 1073922179
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; CHECK-NEXT: xxsplti32dx vs1, 1, 309237645
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; CHECK-NEXT: xsadddp f1, f0, f1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: two_constants:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI11_0@toc@ha
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; CHECK-P9-NEXT: lfd f0, .LCPI11_0@toc@l(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI11_1@toc@ha
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; CHECK-P9-NEXT: xsadddp f0, f1, f0
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; CHECK-P9-NEXT: lfd f1, .LCPI11_1@toc@l(r3)
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; CHECK-P9-NEXT: xsadddp f1, f0, f1
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; CHECK-P9-NEXT: blr
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entry:
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%0 = fadd double %a, 3.344000e+00
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%1 = fadd double %0, 2.344000e+00
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ret double %1
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}
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define double @two_constants_two_bb(i32 %m, double %a) {
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; CHECK-LABEL: two_constants_two_bb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cmplwi r3, 0
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; CHECK-NEXT: beq cr0, .LBB12_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: xxsplti32dx vs1, 0, 1074935889
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; CHECK-NEXT: xxsplti32dx vs1, 1, -343597384
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB12_2: # %if.end
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; CHECK-NEXT: xxsplti32dx vs0, 0, 1076085391
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; CHECK-NEXT: xxsplti32dx vs0, 1, 1546188227
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; CHECK-NEXT: xsadddp f1, f1, f0
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: two_constants_two_bb:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: cmplwi r3, 0
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; CHECK-P9-NEXT: beq cr0, .LBB12_2
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; CHECK-P9-NEXT: # %bb.1:
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; CHECK-P9-NEXT: addis r3, r2, .LCPI12_0@toc@ha
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; CHECK-P9-NEXT: lfd f1, .LCPI12_0@toc@l(r3)
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; CHECK-P9-NEXT: blr
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; CHECK-P9-NEXT: .LBB12_2: # %if.end
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; CHECK-P9-NEXT: addis r3, r2, .LCPI12_1@toc@ha
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; CHECK-P9-NEXT: lfd f0, .LCPI12_1@toc@l(r3)
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; CHECK-P9-NEXT: xsadddp f1, f1, f0
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; CHECK-P9-NEXT: blr
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entry:
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%tobool.not = icmp eq i32 %m, 0
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br i1 %tobool.not, label %if.end, label %return
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if.end:
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%add = fadd double %a, 9.880000e+00
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br label %return
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return:
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%retval.0 = phi double [ %add, %if.end ], [ 4.555000e+00, %entry ]
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ret double %retval.0
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}
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define double @three_constants_f64(double %a, double %c) {
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; CHECK-LABEL: three_constants_f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsplti32dx vs0, 0, 1074446467
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; CHECK-NEXT: xxsplti32dx vs0, 1, 309237645
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; CHECK-NEXT: xsadddp f0, f1, f0
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; CHECK-NEXT: xxsplti32dx vs1, 0, 1073922179
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; CHECK-NEXT: xxsplti32dx vs1, 1, 309237645
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; CHECK-NEXT: xsadddp f0, f0, f1
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; CHECK-NEXT: xxsplti32dx vs1, 0, 1073948393
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; CHECK-NEXT: xxsplti32dx vs1, 1, 2027224564
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; CHECK-NEXT: xsadddp f1, f0, f1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: three_constants_f64:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha
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; CHECK-P9-NEXT: lfd f0, .LCPI13_0@toc@l(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI13_1@toc@ha
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; CHECK-P9-NEXT: xsadddp f0, f1, f0
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; CHECK-P9-NEXT: lfd f1, .LCPI13_1@toc@l(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI13_2@toc@ha
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; CHECK-P9-NEXT: xsadddp f0, f0, f1
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; CHECK-P9-NEXT: lfd f1, .LCPI13_2@toc@l(r3)
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; CHECK-P9-NEXT: xsadddp f1, f0, f1
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; CHECK-P9-NEXT: blr
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entry:
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%0 = fadd double %a, 3.344000e+00
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%1 = fadd double %0, 2.344000e+00
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%2 = fadd double %1, 2.394000e+00
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ret double %2
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}
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define float @three_constants_f32(float %a, float %c) {
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; CHECK-LABEL: three_constants_f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltidp vs0, 1083294351
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; CHECK-NEXT: xsaddsp f0, f1, f0
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; CHECK-NEXT: xxspltidp vs1, 1083296911
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; CHECK-NEXT: xsaddsp f0, f0, f1
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; CHECK-NEXT: xxspltidp vs1, 1083292559
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; CHECK-NEXT: xsaddsp f1, f0, f1
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: three_constants_f32:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI14_0@toc@ha
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; CHECK-P9-NEXT: lfs f0, .LCPI14_0@toc@l(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI14_1@toc@ha
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; CHECK-P9-NEXT: xsaddsp f0, f1, f0
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; CHECK-P9-NEXT: lfs f1, .LCPI14_1@toc@l(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI14_2@toc@ha
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; CHECK-P9-NEXT: xsaddsp f0, f0, f1
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; CHECK-P9-NEXT: lfs f1, .LCPI14_2@toc@l(r3)
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; CHECK-P9-NEXT: xsaddsp f1, f0, f1
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; CHECK-P9-NEXT: blr
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entry:
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%0 = fadd float %a, 0x40123851E0000000
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%1 = fadd float %0, 0x40123991E0000000
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%2 = fadd float %1, 0x40123771E0000000
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ret float %2
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}
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define fp128 @three_constants_f128(fp128 %a, fp128 %c) {
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; CHECK-LABEL: three_constants_f128:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs35, .LCPI15_0@PCREL(0), 1
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: plxv vs35, .LCPI15_1@PCREL(0), 1
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: plxv vs35, .LCPI15_2@PCREL(0), 1
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: three_constants_f128:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l
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; CHECK-P9-NEXT: lxv vs35, 0(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI15_1@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI15_1@toc@l
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; CHECK-P9-NEXT: xsaddqp v2, v2, v3
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; CHECK-P9-NEXT: lxv vs35, 0(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI15_2@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI15_2@toc@l
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; CHECK-P9-NEXT: xsaddqp v2, v2, v3
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; CHECK-P9-NEXT: lxv vs35, 0(r3)
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; CHECK-P9-NEXT: xsaddqp v2, v2, v3
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; CHECK-P9-NEXT: blr
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entry:
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%0 = fadd fp128 %a, 0xL8000000000000000400123851EB851EB
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%1 = fadd fp128 %0, 0xL8000000000000000400123851EB991EB
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%2 = fadd fp128 %1, 0xL8000000000000000400123851EB771EB
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ret fp128 %2
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}
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define ppc_fp128 @three_constants_ppcf128(ppc_fp128 %a, ppc_fp128 %c) {
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; CHECK-LABEL: three_constants_ppcf128:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset v31, -16
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; CHECK-NEXT: xxsplti32dx vs3, 0, 1074935889
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; CHECK-NEXT: xxlxor f4, f4, f4
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; CHECK-NEXT: stxv vs63, 32(r1) # 16-byte Folded Spill
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; CHECK-NEXT: xxsplti32dx vs63, 0, 1074935889
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; CHECK-NEXT: xxsplti32dx vs3, 1, -343597384
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; CHECK-NEXT: bl __gcc_qadd@notoc
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; CHECK-NEXT: xxsplti32dx vs3, 0, 1074935889
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; CHECK-NEXT: xxlxor f4, f4, f4
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; CHECK-NEXT: xxsplti32dx vs3, 1, -1719329096
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; CHECK-NEXT: bl __gcc_qadd@notoc
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; CHECK-NEXT: xxsplti32dx vs63, 1, 8724152
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; CHECK-NEXT: xxlxor f4, f4, f4
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; CHECK-NEXT: xscpsgndp f3, vs63, vs63
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; CHECK-NEXT: bl __gcc_qadd@notoc
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; CHECK-NEXT: lxv vs63, 32(r1) # 16-byte Folded Reload
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; CHECK-NEXT: addi r1, r1, 48
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: three_constants_ppcf128:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: mflr r0
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; CHECK-P9-NEXT: stdu r1, -32(r1)
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; CHECK-P9-NEXT: std r0, 48(r1)
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; CHECK-P9-NEXT: .cfi_def_cfa_offset 32
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; CHECK-P9-NEXT: .cfi_offset lr, 16
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; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha
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; CHECK-P9-NEXT: xxlxor f4, f4, f4
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; CHECK-P9-NEXT: lfd f3, .LCPI16_0@toc@l(r3)
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; CHECK-P9-NEXT: bl __gcc_qadd
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; CHECK-P9-NEXT: nop
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; CHECK-P9-NEXT: addis r3, r2, .LCPI16_1@toc@ha
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; CHECK-P9-NEXT: xxlxor f4, f4, f4
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; CHECK-P9-NEXT: lfd f3, .LCPI16_1@toc@l(r3)
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; CHECK-P9-NEXT: bl __gcc_qadd
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; CHECK-P9-NEXT: nop
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; CHECK-P9-NEXT: addis r3, r2, .LCPI16_2@toc@ha
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; CHECK-P9-NEXT: xxlxor f4, f4, f4
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; CHECK-P9-NEXT: lfd f3, .LCPI16_2@toc@l(r3)
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; CHECK-P9-NEXT: bl __gcc_qadd
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; CHECK-P9-NEXT: nop
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; CHECK-P9-NEXT: addi r1, r1, 32
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; CHECK-P9-NEXT: ld r0, 16(r1)
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; CHECK-P9-NEXT: mtlr r0
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; CHECK-P9-NEXT: blr
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entry:
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%0 = fadd ppc_fp128 %a, 0xM40123851EB851EB80000000000000000
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%1 = fadd ppc_fp128 %0, 0xM4012385199851EB80000000000000000
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%2 = fadd ppc_fp128 %1, 0xM4012385100851EB80000000000000000
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ret ppc_fp128 %2
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}
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define <2 x double> @three_constants_vector(<2 x double> %a, <2 x double> %c) {
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; CHECK-LABEL: three_constants_vector:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: plxv vs0, .LCPI17_0@PCREL(0), 1
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; CHECK-NEXT: plxv vs2, .LCPI17_1@PCREL(0), 1
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; CHECK-NEXT: xvadddp vs1, vs34, vs0
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; CHECK-NEXT: xvadddp vs1, vs1, vs2
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; CHECK-NEXT: xvadddp vs34, vs1, vs0
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; CHECK-NEXT: blr
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;
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; CHECK-P9-LABEL: three_constants_vector:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: addis r3, r2, .LCPI17_0@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI17_0@toc@l
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; CHECK-P9-NEXT: lxv vs0, 0(r3)
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; CHECK-P9-NEXT: addis r3, r2, .LCPI17_1@toc@ha
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; CHECK-P9-NEXT: addi r3, r3, .LCPI17_1@toc@l
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; CHECK-P9-NEXT: lxv vs2, 0(r3)
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; CHECK-P9-NEXT: xvadddp vs1, vs34, vs0
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; CHECK-P9-NEXT: xvadddp vs1, vs1, vs2
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; CHECK-P9-NEXT: xvadddp vs34, vs1, vs0
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; CHECK-P9-NEXT: blr
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entry:
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%0 = fadd <2 x double> %a, <double 4.555000e+00, double 9.880000e+00>
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%1 = fadd <2 x double> %0, <double 4.555000e+00, double 9.980000e+00>
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%2 = fadd <2 x double> %1, <double 4.555000e+00, double 9.880000e+00>
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ret <2 x double> %2
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}
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