67c1c1dbb6
Make __builtin_cpu_{init|supports|is} target independent and provide an
opt-in query for targets that want to support it. Each target is still
responsible for their specific lowering/code-gen. Also provide code-gen
for PowerPC.
I originally proposed this in https://reviews.llvm.org/D152914 and this
addresses the comments I received there.
---------
Co-authored-by: Nemanja Ivanovic <nemanjaivanovic@nemanjas-air.kpn>
Co-authored-by: Nemanja Ivanovic <nemanja@synopsys.com>
115 lines
3.9 KiB
LLVM
115 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-linux-gnu < %s | FileCheck %s \
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; RUN: -check-prefix=BE64
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc-linux-gnu < %s | FileCheck %s \
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; RUN: -check-prefix=BE32
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s \
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; RUN: -check-prefix=LE
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define dso_local signext i32 @test(i32 noundef signext %a) local_unnamed_addr #0 {
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; BE64-LABEL: test:
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; BE64: # %bb.0: # %entry
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; BE64-NEXT: lwz r4, -28772(r13)
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; BE64-NEXT: andis. r4, r4, 128
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; BE64-NEXT: bne cr0, .LBB0_3
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; BE64-NEXT: # %bb.1: # %if.else
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; BE64-NEXT: lwz r4, -28776(r13)
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; BE64-NEXT: andis. r4, r4, 1024
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; BE64-NEXT: bne cr0, .LBB0_4
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; BE64-NEXT: # %bb.2: # %if.else3
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; BE64-NEXT: lwz r4, -28764(r13)
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; BE64-NEXT: cmplwi r4, 39
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; BE64-NEXT: addi r4, r3, 5
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; BE64-NEXT: slwi r3, r3, 1
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; BE64-NEXT: iseleq r3, r3, r4
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; BE64-NEXT: .LBB0_3: # %return
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; BE64-NEXT: extsw r3, r3
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; BE64-NEXT: blr
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; BE64-NEXT: .LBB0_4: # %if.then2
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; BE64-NEXT: addi r3, r3, -5
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; BE64-NEXT: extsw r3, r3
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; BE64-NEXT: blr
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; BE64: .quad __parse_hwcap_and_convert_at_platform
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;
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; BE32-LABEL: test:
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; BE32: # %bb.0: # %entry
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; BE32-NEXT: lwz r4, -28732(r2)
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; BE32-NEXT: andis. r4, r4, 128
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; BE32-NEXT: bnelr cr0
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; BE32-NEXT: # %bb.1: # %if.else
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; BE32-NEXT: lwz r4, -28736(r2)
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; BE32-NEXT: andis. r4, r4, 1024
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; BE32-NEXT: bne cr0, .LBB0_3
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; BE32-NEXT: # %bb.2: # %if.else3
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; BE32-NEXT: lwz r4, -28724(r2)
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; BE32-NEXT: cmplwi r4, 39
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; BE32-NEXT: addi r4, r3, 5
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; BE32-NEXT: slwi r3, r3, 1
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; BE32-NEXT: iseleq r3, r3, r4
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; BE32-NEXT: blr
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; BE32-NEXT: .LBB0_3: # %if.then2
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; BE32-NEXT: addi r3, r3, -5
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; BE32-NEXT: blr
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; BE32: .long __parse_hwcap_and_convert_at_platform
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;
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; LE-LABEL: test:
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; LE: # %bb.0: # %entry
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; LE-NEXT: lwz r4, -28776(r13)
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; LE-NEXT: andis. r4, r4, 128
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; LE-NEXT: bne cr0, .LBB0_3
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; LE-NEXT: # %bb.1: # %if.else
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; LE-NEXT: lwz r4, -28772(r13)
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; LE-NEXT: andis. r4, r4, 1024
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; LE-NEXT: bne cr0, .LBB0_4
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; LE-NEXT: # %bb.2: # %if.else3
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; LE-NEXT: lwz r4, -28764(r13)
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; LE-NEXT: cmplwi r4, 39
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; LE-NEXT: addi r4, r3, 5
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; LE-NEXT: slwi r3, r3, 1
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; LE-NEXT: iseleq r3, r3, r4
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; LE-NEXT: .LBB0_3: # %return
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; LE-NEXT: extsw r3, r3
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; LE-NEXT: blr
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; LE-NEXT: .LBB0_4: # %if.then2
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; LE-NEXT: addi r3, r3, -5
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; LE-NEXT: extsw r3, r3
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; LE-NEXT: blr
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; LE: .quad __parse_hwcap_and_convert_at_platform
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entry:
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%cpu_supports = tail call i32 @llvm.ppc.fixed.addr.ld(i32 2)
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%0 = and i32 %cpu_supports, 8388608
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%.not = icmp eq i32 %0, 0
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br i1 %.not, label %if.else, label %return
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if.else: ; preds = %entry
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%cpu_supports1 = tail call i32 @llvm.ppc.fixed.addr.ld(i32 1)
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%1 = and i32 %cpu_supports1, 67108864
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%.not12 = icmp eq i32 %1, 0
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br i1 %.not12, label %if.else3, label %if.then2
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if.then2: ; preds = %if.else
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%sub = add nsw i32 %a, -5
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br label %return
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if.else3: ; preds = %if.else
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%cpu_is = tail call i32 @llvm.ppc.fixed.addr.ld(i32 3)
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%2 = icmp eq i32 %cpu_is, 39
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br i1 %2, label %if.then4, label %if.end6
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if.then4: ; preds = %if.else3
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%add = shl nsw i32 %a, 1
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br label %return
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if.end6: ; preds = %if.else3
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%add7 = add nsw i32 %a, 5
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br label %return
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return: ; preds = %entry, %if.end6, %if.then4, %if.then2
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%retval.0 = phi i32 [ %sub, %if.then2 ], [ %add, %if.then4 ], [ %add7, %if.end6 ], [ %a, %entry ]
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ret i32 %retval.0
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}
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declare i32 @llvm.ppc.fixed.addr.ld(i32 immarg) #1
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