d0f9553ef5
This patch basically enables fast-isel for AIX 64-bit subtarget (previously enabled only for ELF 64). The initial motivation is to introduce branch folding to AIX generated code for correct debug behavior. I also saw some compiling time improvement in a few LLVM test-suite benchmarks. (toast, dbms, cjpeg, burg, etc.) Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D98844
77 lines
1.6 KiB
LLVM
77 lines
1.6 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; zext
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define i32 @zext_8_32(i8 %a) nounwind {
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; PPC64: zext_8_32
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%r = zext i8 %a to i32
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; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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ret i32 %r
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}
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define i32 @zext_16_32(i16 %a) nounwind {
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; PPC64: zext_16_32
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%r = zext i16 %a to i32
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; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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ret i32 %r
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}
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define i64 @zext_8_64(i8 %a) nounwind {
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; PPC64: zext_8_64
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%r = zext i8 %a to i64
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; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
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ret i64 %r
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}
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define i64 @zext_16_64(i16 %a) nounwind {
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; PPC64: zext_16_64
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%r = zext i16 %a to i64
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; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
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ret i64 %r
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}
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define i64 @zext_32_64(i32 %a) nounwind {
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; PPC64: zext_32_64
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%r = zext i32 %a to i64
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; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
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ret i64 %r
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}
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; sext
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define i32 @sext_8_32(i8 %a) nounwind {
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; PPC64: sext_8_32
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%r = sext i8 %a to i32
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; PPC64: extsb
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ret i32 %r
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}
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define i32 @sext_16_32(i16 %a) nounwind {
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; PPC64: sext_16_32
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%r = sext i16 %a to i32
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; PPC64: extsh
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ret i32 %r
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}
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define i64 @sext_8_64(i8 %a) nounwind {
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; PPC64: sext_8_64
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%r = sext i8 %a to i64
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; PPC64: extsb
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ret i64 %r
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}
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define i64 @sext_16_64(i16 %a) nounwind {
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; PPC64: sext_16_64
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%r = sext i16 %a to i64
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; PPC64: extsh
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ret i64 %r
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}
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define i64 @sext_32_64(i32 %a) nounwind {
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; PPC64: sext_32_64
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%r = sext i32 %a to i64
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; PPC64: extsw
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ret i64 %r
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}
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