0d253bbd33
Inputs to crnor can come from operands with chains so if it is being used simply to negate such an operand, the repeated input cannot be CSE'd. This patch just adds a code-gen only instruction for this that takes a single input and duplicates it in the encoding of the underlying crnor. Differential revision: https://reviews.llvm.org/D133577
119 lines
4.0 KiB
LLVM
119 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr9 -O0 | FileCheck %s
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define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
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; CHECK-LABEL: une_ppcf128:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fcmpu cr0, f1, f3
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; CHECK-NEXT: crmove 4*cr5+lt, eq
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; CHECK-NEXT: fcmpu cr1, f2, f4
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; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+eq
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; CHECK-NEXT: crnot 4*cr5+gt, 4*cr5+gt
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; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt
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; CHECK-NEXT: crmove 4*cr5+lt, eq
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; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
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; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
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; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
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; CHECK-NEXT: li r4, 0
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%0 = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
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%1 = zext i1 %0 to i32
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ret i32 %1
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}
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; This is a different branch from une
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define i32 @ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
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; CHECK-LABEL: ogt_ppcf128:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fcmpu cr0, f1, f3
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; CHECK-NEXT: crmove 4*cr5+lt, eq
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; CHECK-NEXT: fcmpu cr1, f2, f4
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; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+gt
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; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt
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; CHECK-NEXT: crmove 4*cr5+lt, eq
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; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
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; CHECK-NEXT: crmove 4*cr5+eq, gt
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; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+eq
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; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
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; CHECK-NEXT: li r4, 0
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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entry:
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%0 = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #0
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%1 = zext i1 %0 to i32
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ret i32 %1
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}
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define i1 @test_f128(fp128 %a, fp128 %b) #0 {
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; CHECK-LABEL: test_f128:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscmpuqp cr0, v2, v3
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; CHECK-NEXT: crmove 4*cr5+lt, eq
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; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
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; CHECK-NEXT: li r4, 0
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
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; CHECK-NEXT: blr
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entry:
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%0 = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
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ret i1 %0
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}
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define i1 @testbr_f64(double %a, double %b) #0 {
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; CHECK-LABEL: testbr_f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fcmpu cr0, f1, f2
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; CHECK-NEXT: crmove 4*cr5+lt, eq
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB3_2
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; CHECK-NEXT: b .LBB3_1
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; CHECK-NEXT: .LBB3_1: # %tr
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; CHECK-NEXT: li r3, -1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB3_2: # %fl
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: blr
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entry:
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%0 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") #0
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br i1 %0, label %tr, label %fl
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tr:
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ret i1 true
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fl:
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ret i1 false
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}
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define i1 @testbr_f32(float %a, float %b) #0 {
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; CHECK-LABEL: testbr_f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fcmpu cr0, f1, f2
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; CHECK-NEXT: crmove 4*cr5+lt, eq
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB4_2
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; CHECK-NEXT: b .LBB4_1
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; CHECK-NEXT: .LBB4_1: # %tr
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; CHECK-NEXT: li r3, -1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB4_2: # %fl
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: blr
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entry:
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%0 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") #0
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br i1 %0, label %tr, label %fl
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tr:
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ret i1 true
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fl:
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ret i1 false
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}
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declare i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128, ppc_fp128, metadata, metadata)
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declare i1 @llvm.experimental.constrained.fcmp.f128(fp128, fp128, metadata, metadata)
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declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
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declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
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attributes #0 = { strictfp }
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