a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
121 lines
4.0 KiB
LLVM
121 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
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; RUN: 2>&1 | FileCheck --check-prefix=CHECK-LE %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=ppc < %s \
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; RUN: 2>&1 | FileCheck --check-prefix=CHECK-BE %s
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%0 = type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, [8 x i8] }>
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@global.1 = internal global %0 <{ i32 129, i32 2, i32 118, i32 0, i32 5, i32 0, i32 0, i32 0, i32 120, i32 0, ptr @global.2, [8 x i8] c"\00\00\00\00\00\00\00\03" }>, align 4
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@global.2 = internal constant [3 x i8] c"x.c"
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@alias = dso_local alias i32 (), ptr @main
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define dso_local signext i32 @main() nounwind {
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; CHECK-LE-LABEL: main:
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; CHECK-LE: # %bb.0: # %bb
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; CHECK-LE-NEXT: mflr 0
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; CHECK-LE-NEXT: std 0, 16(1)
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; CHECK-LE-NEXT: lis 0, -1
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; CHECK-LE-NEXT: ori 0, 0, 65535
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; CHECK-LE-NEXT: sldi 0, 0, 32
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; CHECK-LE-NEXT: oris 0, 0, 32767
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; CHECK-LE-NEXT: ori 0, 0, 65120
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; CHECK-LE-NEXT: stdux 1, 1, 0
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; CHECK-LE-NEXT: lis 3, 0
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; CHECK-LE-NEXT: sldi 3, 3, 32
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; CHECK-LE-NEXT: oris 3, 3, 32768
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; CHECK-LE-NEXT: ori 3, 3, 400
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; CHECK-LE-NEXT: stdx 30, 1, 3 # 8-byte Folded Spill
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; CHECK-LE-NEXT: bl pluto
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; CHECK-LE-NEXT: nop
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; CHECK-LE-NEXT: addis 3, 2, global.1@toc@ha
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; CHECK-LE-NEXT: li 4, 257
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; CHECK-LE-NEXT: li 7, 0
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; CHECK-LE-NEXT: li 8, 0
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; CHECK-LE-NEXT: li 9, 0
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; CHECK-LE-NEXT: addi 5, 3, global.1@toc@l
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; CHECK-LE-NEXT: li 3, 0
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; CHECK-LE-NEXT: ori 6, 3, 32768
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; CHECK-LE-NEXT: li 3, 6
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; CHECK-LE-NEXT: bl snork
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; CHECK-LE-NEXT: nop
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; CHECK-LE-NEXT: mr 30, 3
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; CHECK-LE-NEXT: li 3, 344
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; CHECK-LE-NEXT: addi 4, 1, 48
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; CHECK-LE-NEXT: li 5, 8
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; CHECK-LE-NEXT: li 6, 8
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; CHECK-LE-NEXT: oris 3, 3, 32768
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; CHECK-LE-NEXT: add 4, 4, 3
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; CHECK-LE-NEXT: mr 3, 30
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; CHECK-LE-NEXT: bl zot
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; CHECK-LE-NEXT: nop
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; CHECK-LE-NEXT: mr 3, 30
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; CHECK-LE-NEXT: bl wibble
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; CHECK-LE-NEXT: nop
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; CHECK-LE-NEXT: li 3, 0
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; CHECK-LE-NEXT: bl snork.3
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; CHECK-LE-NEXT: nop
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;
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; CHECK-BE-LABEL: main:
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; CHECK-BE: # %bb.0: # %bb
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; CHECK-BE-NEXT: mflr 0
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; CHECK-BE-NEXT: std 0, 16(1)
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; CHECK-BE-NEXT: lis 0, -1
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; CHECK-BE-NEXT: ori 0, 0, 65535
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; CHECK-BE-NEXT: sldi 0, 0, 32
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; CHECK-BE-NEXT: oris 0, 0, 32767
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; CHECK-BE-NEXT: ori 0, 0, 65056
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; CHECK-BE-NEXT: stdux 1, 1, 0
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; CHECK-BE-NEXT: lis 3, 0
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; CHECK-BE-NEXT: sldi 3, 3, 32
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; CHECK-BE-NEXT: oris 3, 3, 32768
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; CHECK-BE-NEXT: ori 3, 3, 472
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; CHECK-BE-NEXT: stdx 31, 1, 3 # 8-byte Folded Spill
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; CHECK-BE-NEXT: bl .pluto[PR]
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: ld 5, L..C0(2) # @global.1
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; CHECK-BE-NEXT: li 3, 0
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; CHECK-BE-NEXT: ori 6, 3, 32768
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; CHECK-BE-NEXT: li 3, 6
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; CHECK-BE-NEXT: li 4, 257
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; CHECK-BE-NEXT: li 7, 0
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; CHECK-BE-NEXT: li 8, 0
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; CHECK-BE-NEXT: li 9, 0
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; CHECK-BE-NEXT: bl .snork[PR]
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: mr 31, 3
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; CHECK-BE-NEXT: li 3, 344
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; CHECK-BE-NEXT: oris 3, 3, 32768
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; CHECK-BE-NEXT: addi 4, 1, 120
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; CHECK-BE-NEXT: add 4, 4, 3
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; CHECK-BE-NEXT: mr 3, 31
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; CHECK-BE-NEXT: li 5, 8
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; CHECK-BE-NEXT: li 6, 8
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; CHECK-BE-NEXT: bl .zot[PR]
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: mr 3, 31
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; CHECK-BE-NEXT: bl .wibble[PR]
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: li 3, 0
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; CHECK-BE-NEXT: bl .snork.3[PR]
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; CHECK-BE-NEXT: nop
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bb:
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%tmp = alloca [2147484000 x i8], align 8
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tail call void @pluto()
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%tmp6 = tail call i64 @snork(i64 6, i32 257, ptr nonnull @global.1, i64 32768, ptr null, i64 0, ptr null)
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%tmp7 = getelementptr inbounds [2147484000 x i8], ptr %tmp, i64 0, i64 2147483992
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%tmp9 = call i64 @zot(i64 %tmp6, ptr nonnull %tmp7, i64 8, i64 8)
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%tmp10 = call i64 @wibble(i64 %tmp6)
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call void @snork.3(i64 0)
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unreachable
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}
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declare void @pluto()
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declare signext i64 @snork(i64, i32, ptr, i64, ptr, i64, ptr)
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declare signext i64 @zot(i64, ptr, i64, i64)
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declare signext i64 @wibble(i64)
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declare void @snork.3(i64)
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