1492c88f49
This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass. - Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer). - Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D40554
63 lines
2.4 KiB
LLVM
63 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
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; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-32
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define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vcmpgtsw. 2, 2, 3
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; CHECK-NEXT: bge 6, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %land.rhs
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; CHECK-NEXT: vcmpgtsw. 2, 4, 3
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; CHECK-NEXT: mfocrf 3, 2
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; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: blr
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;
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; CHECK-AIX-64-LABEL: test:
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; CHECK-AIX-64: # %bb.0: # %entry
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; CHECK-AIX-64-NEXT: vcmpgtsw. 2, 2, 3
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; CHECK-AIX-64-NEXT: bge 6, L..BB0_2
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; CHECK-AIX-64-NEXT: # %bb.1: # %land.rhs
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; CHECK-AIX-64-NEXT: vcmpgtsw. 2, 4, 3
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; CHECK-AIX-64-NEXT: mfocrf 3, 2
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; CHECK-AIX-64-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-AIX-64-NEXT: blr
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; CHECK-AIX-64-NEXT: L..BB0_2:
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; CHECK-AIX-64-NEXT: li 3, 0
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; CHECK-AIX-64-NEXT: blr
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;
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; CHECK-AIX-32-LABEL: test:
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; CHECK-AIX-32: # %bb.0: # %entry
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; CHECK-AIX-32-NEXT: vcmpgtsw. 2, 2, 3
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; CHECK-AIX-32-NEXT: bge 6, L..BB0_2
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; CHECK-AIX-32-NEXT: # %bb.1: # %land.rhs
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; CHECK-AIX-32-NEXT: vcmpgtsw. 2, 4, 3
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; CHECK-AIX-32-NEXT: mfocrf 3, 2
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; CHECK-AIX-32-NEXT: rlwinm 3, 3, 25, 31, 31
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; CHECK-AIX-32-NEXT: blr
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; CHECK-AIX-32-NEXT: L..BB0_2:
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; CHECK-AIX-32-NEXT: li 3, 0
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; CHECK-AIX-32-NEXT: blr
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entry:
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%0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b)
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%tobool.not = icmp eq i32 %0, 0
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br i1 %tobool.not, label %land.end, label %land.rhs
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land.rhs: ; preds = %entry
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%1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x i32> %b)
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%tobool1 = icmp ne i32 %1, 0
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%phi.cast = zext i1 %tobool1 to i32
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br label %land.end
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land.end: ; preds = %land.rhs, %entry
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%2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
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ret i32 %2
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}
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declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
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