a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
116 lines
3.8 KiB
LLVM
116 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s
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; RUN: llc -enable-ppc-gen-scalar-mass -O3 -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s
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define void @cos_f64(ptr %arg) {
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; CHECK-LNX-LABEL: cos_f64:
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; CHECK-LNX: # %bb.0: # %bb
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; CHECK-LNX-NEXT: mflr 0
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; CHECK-LNX-NEXT: stdu 1, -32(1)
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; CHECK-LNX-NEXT: std 0, 48(1)
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; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
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; CHECK-LNX-NEXT: .cfi_offset lr, 16
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; CHECK-LNX-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-LNX-NEXT: lfs 1, .LCPI0_0@toc@l(3)
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; CHECK-LNX-NEXT: bl __xl_cos_finite
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; CHECK-LNX-NEXT: nop
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; CHECK-LNX-NEXT: xssqrtdp 0, 0
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; CHECK-LNX-NEXT: xsmuldp 0, 0, 1
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; CHECK-LNX-NEXT: .p2align 4
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; CHECK-LNX-NEXT: .LBB0_1: # %bb2
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; CHECK-LNX-NEXT: #
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; CHECK-LNX-NEXT: stfd 0, 0(3)
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; CHECK-LNX-NEXT: b .LBB0_1
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;
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; CHECK-AIX-LABEL: cos_f64:
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; CHECK-AIX: # %bb.0: # %bb
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; CHECK-AIX-NEXT: mflr 0
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; CHECK-AIX-NEXT: stwu 1, -64(1)
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; CHECK-AIX-NEXT: stw 0, 72(1)
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; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
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; CHECK-AIX-NEXT: bl .sqrt[PR]
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; CHECK-AIX-NEXT: nop
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; CHECK-AIX-NEXT: lwz 3, L..C0(2) # %const.0
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; CHECK-AIX-NEXT: fmr 31, 1
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; CHECK-AIX-NEXT: lfs 0, 0(3)
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; CHECK-AIX-NEXT: fmr 1, 0
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; CHECK-AIX-NEXT: bl .__xl_cos_finite[PR]
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; CHECK-AIX-NEXT: nop
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; CHECK-AIX-NEXT: fmul 0, 31, 1
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; CHECK-AIX-NEXT: L..BB0_1: # %bb2
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; CHECK-AIX-NEXT: #
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; CHECK-AIX-NEXT: stfd 0, 0(3)
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; CHECK-AIX-NEXT: b L..BB0_1
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bb:
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%i1 = getelementptr i8, ptr %arg, i64 undef
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br label %bb2
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bb2:
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%i3 = getelementptr inbounds i8, ptr %i1, i64 undef
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store double undef, ptr %i3, align 8
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%i7 = tail call fast double @llvm.sqrt.f64(double undef)
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%i8 = fmul fast double undef, 0x401921FB54442D28
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%i9 = tail call fast double @llvm.cos.f64(double %i8) #2
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%i10 = fmul fast double %i7, %i9
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store double %i10, ptr %i1, align 8
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br label %bb2
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}
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define void @log_f64(ptr %arg) {
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; CHECK-LNX-LABEL: log_f64:
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; CHECK-LNX: # %bb.0: # %bb
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; CHECK-LNX-NEXT: mflr 0
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; CHECK-LNX-NEXT: stdu 1, -32(1)
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; CHECK-LNX-NEXT: std 0, 48(1)
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; CHECK-LNX-NEXT: .cfi_def_cfa_offset 32
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; CHECK-LNX-NEXT: .cfi_offset lr, 16
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; CHECK-LNX-NEXT: addis 3, 2, .LCPI1_0@toc@ha
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; CHECK-LNX-NEXT: lfs 1, .LCPI1_0@toc@l(3)
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; CHECK-LNX-NEXT: bl __xl_log_finite
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; CHECK-LNX-NEXT: nop
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; CHECK-LNX-NEXT: xssqrtdp 0, 0
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; CHECK-LNX-NEXT: xsmuldp 0, 0, 1
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; CHECK-LNX-NEXT: .p2align 4
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; CHECK-LNX-NEXT: .LBB1_1: # %bb2
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; CHECK-LNX-NEXT: #
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; CHECK-LNX-NEXT: stfd 0, 0(3)
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; CHECK-LNX-NEXT: b .LBB1_1
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;
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; CHECK-AIX-LABEL: log_f64:
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; CHECK-AIX: # %bb.0: # %bb
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; CHECK-AIX-NEXT: mflr 0
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; CHECK-AIX-NEXT: stwu 1, -64(1)
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; CHECK-AIX-NEXT: stw 0, 72(1)
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; CHECK-AIX-NEXT: stfd 31, 56(1) # 8-byte Folded Spill
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; CHECK-AIX-NEXT: bl .sqrt[PR]
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; CHECK-AIX-NEXT: nop
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; CHECK-AIX-NEXT: lwz 3, L..C1(2) # %const.0
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; CHECK-AIX-NEXT: fmr 31, 1
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; CHECK-AIX-NEXT: lfs 0, 0(3)
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; CHECK-AIX-NEXT: fmr 1, 0
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; CHECK-AIX-NEXT: bl .__xl_log_finite[PR]
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; CHECK-AIX-NEXT: nop
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; CHECK-AIX-NEXT: fmul 0, 31, 1
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; CHECK-AIX-NEXT: L..BB1_1: # %bb2
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; CHECK-AIX-NEXT: #
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; CHECK-AIX-NEXT: stfd 0, 0(3)
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; CHECK-AIX-NEXT: b L..BB1_1
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bb:
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%i1 = getelementptr i8, ptr %arg, i64 undef
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br label %bb2
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bb2:
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%i3 = getelementptr inbounds i8, ptr %i1, i64 undef
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store double undef, ptr %i3, align 8
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%i7 = tail call fast double @llvm.sqrt.f64(double undef)
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%i8 = fmul fast double undef, 0x401921FB54442D28
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%i9 = tail call fast double @llvm.log.f64(double %i8) #2
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%i10 = fmul fast double %i7, %i9
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store double %i10, ptr %i1, align 8
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br label %bb2
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}
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declare double @llvm.sqrt.f64(double)
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declare double @llvm.cos.f64(double)
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declare double @llvm.log.f64(double)
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