4dfea22e77
AArch64 and PowerPC look like a improvements. RISC-V is neutral. X86 trades a dependency breaking xor before a seta for a movsx after a sbbb. Depending on how the result is used, this movsx might go away.
61 lines
1.9 KiB
LLVM
61 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK
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define signext i32 @memcmp8(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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; CHECK-LABEL: memcmp8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ldbrx 3, 0, 3
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; CHECK-NEXT: ldbrx 4, 0, 4
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; CHECK-NEXT: cmpld 3, 4
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; CHECK-NEXT: subc 3, 4, 3
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; CHECK-NEXT: subfe 3, 4, 4
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; CHECK-NEXT: li 4, -1
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; CHECK-NEXT: neg 3, 3
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; CHECK-NEXT: isellt 3, 4, 3
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 8)
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ret i32 %call
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}
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define signext i32 @memcmp4(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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; CHECK-LABEL: memcmp4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lwbrx 3, 0, 3
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; CHECK-NEXT: lwbrx 4, 0, 4
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; CHECK-NEXT: cmplw 3, 4
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; CHECK-NEXT: sub 5, 4, 3
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: rldicl 5, 5, 1, 63
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; CHECK-NEXT: isellt 3, 3, 5
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 4)
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ret i32 %call
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}
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define signext i32 @memcmp2(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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; CHECK-LABEL: memcmp2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lhbrx 3, 0, 3
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; CHECK-NEXT: lhbrx 4, 0, 4
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; CHECK-NEXT: sub 3, 3, 4
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 2)
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ret i32 %call
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}
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define signext i32 @memcmp1(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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; CHECK-LABEL: memcmp1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lbz 3, 0(3)
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; CHECK-NEXT: lbz 4, 0(4)
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; CHECK-NEXT: sub 3, 3, 4
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 1) #2
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ret i32 %call
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}
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declare signext i32 @memcmp(ptr, ptr, i64)
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