5dc0a1657b
The `__builtin_pdepd` and `__builtin_pextd` are P10 builtins that are meant to
be used under 64-bit only. For instance, when the builtins are compiled under
32-bit mode:
```
$ cat t.c
unsigned long long foo(unsigned long long a, unsigned long long b) {
return __builtin_pextd(a,b);
}
$ clang -c t.c -mcpu=pwr10 -m32
ExpandIntegerResult #0: t31: i64 = llvm.ppc.pextd TargetConstant:i32<6928>, t28, t29
fatal error: error in backend: Do not know how to expand the result of this operator!
```
This patch adds sema checking for these builtins to compile under 64-bit
mode only and on P10. The builtins will emit a diagnostic when they are compiled on
non-P10 compilations and on 32-bit mode.
Differential Revision: https://reviews.llvm.org/D118753
163 lines
4.8 KiB
LLVM
163 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; These test cases aim to test the bit manipulation operations on Power10.
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declare <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.pdepd(i64, i64)
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declare i64 @llvm.ppc.pextd(i64, i64)
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declare <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.cfuged(i64, i64)
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declare i64 @llvm.ppc.altivec.vgnb(<1 x i128>, i32)
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declare <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64>, <2 x i64>, <2 x i64>, i32)
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declare <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64>, <2 x i64>)
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declare i64 @llvm.ppc.cntlzdm(i64, i64)
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declare i64 @llvm.ppc.cnttzdm(i64, i64)
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define <2 x i64> @test_vpdepd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vpdepd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vpdepd v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define <2 x i64> @test_vpextd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vpextd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vpextd v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define i64 @test_pdepd(i64 %a, i64 %b) {
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; CHECK-LABEL: test_pdepd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pdepd r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.pdepd(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @test_pextd(i64 %a, i64 %b) {
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; CHECK-LABEL: test_pextd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pextd r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.pextd(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define <2 x i64> @test_vcfuged(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vcfuged:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vcfuged v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define i64 @test_cfuged(i64 %a, i64 %b) {
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; CHECK-LABEL: test_cfuged:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cfuged r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.cfuged(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @test_vgnb_1(<1 x i128> %a) {
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; CHECK-LABEL: test_vgnb_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vgnb r3, v2, 2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 2)
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ret i64 %tmp
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}
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define i64 @test_vgnb_2(<1 x i128> %a) {
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; CHECK-LABEL: test_vgnb_2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vgnb r3, v2, 7
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 7)
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ret i64 %tmp
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}
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define i64 @test_vgnb_3(<1 x i128> %a) {
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; CHECK-LABEL: test_vgnb_3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vgnb r3, v2, 5
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 5)
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ret i64 %tmp
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}
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define <2 x i64> @test_xxeval(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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; CHECK-LABEL: test_xxeval:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxeval v2, v2, v3, v4, 255
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, i32 255)
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ret <2 x i64> %tmp
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}
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define <2 x i64> @test_vclzdm(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vclzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vclzdm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define <2 x i64> @test_vctzdm(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vctzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vctzdm v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %tmp
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}
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define i64 @test_cntlzdm(i64 %a, i64 %b) {
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; CHECK-LABEL: test_cntlzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cntlzdm r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.cntlzdm(i64 %a, i64 %b)
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ret i64 %tmp
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}
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define i64 @test_cnttzdm(i64 %a, i64 %b) {
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; CHECK-LABEL: test_cnttzdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cnttzdm r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i64 @llvm.ppc.cnttzdm(i64 %a, i64 %b)
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ret i64 %tmp
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}
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