8e901c255d
We can decide whether to expand isel or not in instruction selection pass and early-if-conversion pass. The transformation implemented in PPCExpandISel can be retired considering PPC backend doesn't generate `isel` instructions post-RA. Also if we are seeking performant branch-or-isel decision, we can turn to selectoptimize pass. --------- Co-authored-by: Kai Luo <lkail@cn.ibm.com>
78 lines
2.8 KiB
LLVM
78 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define void @foo(ptr nocapture %r1, ptr nocapture %r2, ptr nocapture %r3, ptr nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 {
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; Make sure that we don't schedule all of the isels together, they should be
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; intermixed with the adds because each isel starts a new dispatch group.
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cmplwi 7, 0
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; CHECK-NEXT: addi 7, 8, 1
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; CHECK-NEXT: iseleq 9, 9, 8
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; CHECK-NEXT: stw 9, 0(3)
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; CHECK-NEXT: addi 3, 10, -2
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; CHECK-NEXT: iseleq 9, 10, 8
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; CHECK-NEXT: iseleq 3, 3, 7
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; CHECK-NEXT: stw 9, 0(4)
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; CHECK-NEXT: addi 4, 10, -5
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; CHECK-NEXT: stw 3, 0(5)
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; CHECK-NEXT: addi 3, 8, 3
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: stw 3, 0(6)
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; CHECK-NEXT: blr
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;
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; CHECK-NO-ISEL-LABEL: foo:
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; CHECK-NO-ISEL: # %bb.0: # %entry
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; CHECK-NO-ISEL-NEXT: cmplwi 7, 0
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; CHECK-NO-ISEL-NEXT: mr 7, 8
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; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_2
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; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
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; CHECK-NO-ISEL-NEXT: mr 7, 9
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; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry
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; CHECK-NO-ISEL-NEXT: stw 7, 0(3)
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; CHECK-NO-ISEL-NEXT: mr 3, 8
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; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_4
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; CHECK-NO-ISEL-NEXT: # %bb.3: # %entry
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; CHECK-NO-ISEL-NEXT: mr 3, 10
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; CHECK-NO-ISEL-NEXT: .LBB0_4: # %entry
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; CHECK-NO-ISEL-NEXT: stw 3, 0(4)
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; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_7
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; CHECK-NO-ISEL-NEXT: # %bb.5: # %entry
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; CHECK-NO-ISEL-NEXT: addi 3, 10, -2
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; CHECK-NO-ISEL-NEXT: stw 3, 0(5)
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; CHECK-NO-ISEL-NEXT: beq 0, .LBB0_8
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; CHECK-NO-ISEL-NEXT: .LBB0_6:
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; CHECK-NO-ISEL-NEXT: addi 3, 8, 3
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; CHECK-NO-ISEL-NEXT: stw 3, 0(6)
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; CHECK-NO-ISEL-NEXT: blr
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; CHECK-NO-ISEL-NEXT: .LBB0_7:
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; CHECK-NO-ISEL-NEXT: addi 3, 8, 1
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; CHECK-NO-ISEL-NEXT: stw 3, 0(5)
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; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_6
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; CHECK-NO-ISEL-NEXT: .LBB0_8: # %entry
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; CHECK-NO-ISEL-NEXT: addi 3, 10, -5
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; CHECK-NO-ISEL-NEXT: stw 3, 0(6)
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; CHECK-NO-ISEL-NEXT: blr
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entry:
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%tobool = icmp ne i32 %a, 0
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%cond = select i1 %tobool, i32 %b, i32 %c
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store i32 %cond, ptr %r1, align 4
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%cond5 = select i1 %tobool, i32 %b, i32 %d
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store i32 %cond5, ptr %r2, align 4
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%add = add nsw i32 %b, 1
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%sub = add nsw i32 %d, -2
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%cond10 = select i1 %tobool, i32 %add, i32 %sub
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store i32 %cond10, ptr %r3, align 4
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%add13 = add nsw i32 %b, 3
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%sub15 = add nsw i32 %d, -5
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%cond17 = select i1 %tobool, i32 %add13, i32 %sub15
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store i32 %cond17, ptr %r4, align 4
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ret void
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}
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attributes #0 = { nounwind }
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