082c5d7f63
mffsl is available since ISA 3.0. The builtin is named with ppc prefix to follow our convention. For targets earlier than power9, GCC generates extra code to support the functionality, while this patch does not implement such behavior. Reviewed By: nemanjai, tuliom Differential Revision: https://reviews.llvm.org/D158065
171 lines
5.9 KiB
LLVM
171 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple powerpc64le-unknown-linux | FileCheck %s
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; RUN: llc < %s -mtriple powerpc64le-unknown-linux -debug-only=machine-scheduler \
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; RUN: 2>&1 | FileCheck %s --check-prefix=LOG
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; REQUIRES: asserts
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define double @in_nostrict(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: in_nostrict:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: xsdivdp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 1, 3
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; CHECK-NEXT: xsadddp 0, 1, 0
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; CHECK-NEXT: mtfsf 255, 4
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; CHECK-NEXT: xsdivdp 1, 3, 4
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; CHECK-NEXT: xsadddp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 0, 1
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; CHECK-NEXT: blr
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;
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; LOG: *** MI Scheduling ***
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; LOG-NEXT: in_nostrict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, %{{[0-9]+}}:f8rc, 0, 0
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; LOG: *** MI Scheduling ***
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; LOG-NEXT: in_nostrict:%bb.0 entry
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; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
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;
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; LOG: *** MI Scheduling ***
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; LOG-NEXT: in_nostrict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, renamable $f{{[0-9]+}}, 0, 0
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entry:
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%0 = tail call double @llvm.ppc.readflm()
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%1 = fdiv double %a, %b
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%2 = fadd double %1, %c
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%3 = fadd double %2, %0
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call double @llvm.ppc.setflm(double %d)
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%5 = fdiv double %c, %d
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%6 = fadd double %5, %b
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%7 = fadd double %3, %6
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ret double %7
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}
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define double @in_strict(double %a, double %b, double %c, double %d) #0 {
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; CHECK-LABEL: in_strict:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: xsdivdp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 1, 3
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; CHECK-NEXT: xsadddp 0, 1, 0
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; CHECK-NEXT: mtfsf 255, 4
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; CHECK-NEXT: xsdivdp 1, 3, 4
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; CHECK-NEXT: xsadddp 1, 1, 2
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; CHECK-NEXT: xsadddp 1, 0, 1
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; CHECK-NEXT: blr
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;
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; LOG: ***** MI Scheduling *****
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; LOG-NEXT: in_strict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, %{{[0-9]+}}:f8rc, 0, 0
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; LOG: ***** MI Scheduling *****
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; LOG-NEXT: in_strict:%bb.0 entry
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; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
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;
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; LOG: ***** MI Scheduling *****
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; LOG-NEXT: in_strict:%bb.0 entry
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; LOG: ExitSU: MTFSF 255, renamable $f{{[0-9]+}}, 0, 0
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entry:
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%0 = tail call double @llvm.ppc.readflm()
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%1 = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%2 = call double @llvm.experimental.constrained.fadd.f64(double %1, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%3 = call double @llvm.experimental.constrained.fadd.f64(double %2, double %0, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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call double @llvm.ppc.setflm(double %d)
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%5 = call double @llvm.experimental.constrained.fdiv.f64(double %c, double %d, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%6 = call double @llvm.experimental.constrained.fadd.f64(double %5, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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%7 = call double @llvm.experimental.constrained.fadd.f64(double %3, double %6, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
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ret double %7
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}
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define void @cse_nomerge(ptr %f1, ptr %f2, double %f3) #0 {
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; CHECK-LABEL: cse_nomerge:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r30, -24
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; CHECK-NEXT: .cfi_offset f31, -8
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; CHECK-NEXT: std 30, -24(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu 1, -64(1)
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; CHECK-NEXT: std 0, 80(1)
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; CHECK-NEXT: fmr 31, 1
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; CHECK-NEXT: mr 30, 4
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: stfd 0, 0(3)
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; CHECK-NEXT: bl effect_func
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; CHECK-NEXT: nop
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: stfd 0, 0(30)
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; CHECK-NEXT: mtfsf 255, 31
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; CHECK-NEXT: addi 1, 1, 64
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 30, -24(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%0 = call double @llvm.ppc.readflm()
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store double %0, ptr %f1, align 8
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call void @effect_func()
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%1 = call double @llvm.ppc.readflm()
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store double %1, ptr %f2, align 8
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%2 = call contract double @llvm.ppc.setflm(double %f3)
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ret void
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}
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define void @cse_nomerge_readonly(ptr %f1, ptr %f2, double %f3) #0 {
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; CHECK-LABEL: cse_nomerge_readonly:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r30, -24
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; CHECK-NEXT: .cfi_offset f31, -8
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; CHECK-NEXT: std 30, -24(1) # 8-byte Folded Spill
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; CHECK-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu 1, -64(1)
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; CHECK-NEXT: std 0, 80(1)
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; CHECK-NEXT: fmr 31, 1
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; CHECK-NEXT: mr 30, 4
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: stfd 0, 0(3)
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; CHECK-NEXT: bl readonly_func
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; CHECK-NEXT: nop
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; CHECK-NEXT: mffs 0
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; CHECK-NEXT: stfd 0, 0(30)
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; CHECK-NEXT: mtfsf 255, 31
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; CHECK-NEXT: addi 1, 1, 64
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
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; CHECK-NEXT: ld 30, -24(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%0 = call double @llvm.ppc.readflm()
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store double %0, ptr %f1, align 8
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call void @readonly_func()
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%1 = call double @llvm.ppc.readflm()
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store double %1, ptr %f2, align 8
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%2 = call contract double @llvm.ppc.setflm(double %f3)
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ret void
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}
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define double @mffsl() {
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; CHECK-LABEL: mffsl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mffsl 1
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; CHECK-NEXT: blr
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entry:
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%x = call double @llvm.ppc.mffsl()
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ret double %x
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}
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declare void @effect_func()
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declare void @readonly_func() #1
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declare double @llvm.ppc.mffsl()
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declare double @llvm.ppc.readflm()
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declare double @llvm.ppc.setflm(double)
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declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
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declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
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attributes #0 = { strictfp }
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attributes #1 = { readonly }
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