a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
207 lines
5.0 KiB
LLVM
207 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=generic -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "E-m:a-p:32:32-i64:64-n32"
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target triple = "powerpc-ibm-aix7.2.0.0"
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%struct.USST = type { i16, i16 }
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%struct.SST = type { i16, i16 }
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%struct.CST = type { i8, i8 }
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%struct.SCST = type { i8, i8 }
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%struct.ST = type { i32, i32 }
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%struct.UST = type { i32, i32 }
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; Function Attrs: nounwind
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define i32 @ustc1(ptr noundef byval(%struct.USST) align 4 %s) {
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; CHECK-LABEL: ustc1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 4, 3
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; CHECK-NEXT: srwi 3, 3, 24
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; CHECK-NEXT: stw 4, 24(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i16, ptr %s, align 4
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%conv = zext i16 %0 to i32
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%shr = ashr i32 %conv, 8
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ret i32 %shr
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}
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; Function Attrs: nounwind
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define i32 @ustc2(ptr noundef byval(%struct.USST) align 4 %s) {
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; CHECK-LABEL: ustc2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 4, 3
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; CHECK-NEXT: srwi 3, 3, 16
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; CHECK-NEXT: stw 4, 24(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i16, ptr %s, align 4
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%conv = zext i16 %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define i32 @stc1(ptr noundef byval(%struct.SST) align 4 %s) {
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; CHECK-LABEL: stc1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 4, 3
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; CHECK-NEXT: srawi 3, 3, 24
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; CHECK-NEXT: stw 4, 24(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i16, ptr %s, align 4
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%conv = sext i16 %0 to i32
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%shr = ashr i32 %conv, 8
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ret i32 %shr
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}
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; Function Attrs: nounwind
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define i32 @stc2(ptr noundef byval(%struct.SST) align 4 %s) {
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; CHECK-LABEL: stc2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 4, 3
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; CHECK-NEXT: srawi 3, 3, 16
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; CHECK-NEXT: stw 4, 24(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i16, ptr %s, align 4
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%conv = sext i16 %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define i32 @ctc(ptr noundef byval(%struct.CST) align 4 %s) {
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; CHECK-LABEL: ctc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 4, 3
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; CHECK-NEXT: srwi 3, 3, 24
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; CHECK-NEXT: stw 4, 24(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i8, ptr %s, align 4
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define i32 @sctc(ptr noundef byval(%struct.SCST) align 4 %s) {
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; CHECK-LABEL: sctc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mr 4, 3
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; CHECK-NEXT: srawi 3, 3, 24
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; CHECK-NEXT: stw 4, 24(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i8, ptr %s, align 4
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%conv = sext i8 %0 to i32
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ret i32 %conv
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}
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; Function Attrs: nounwind
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define i32 @tc44(ptr noundef byval(%struct.ST) align 4 %s) {
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; CHECK-LABEL: tc44:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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ret i32 %0
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}
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; Function Attrs: nounwind
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define i32 @tc41(ptr noundef byval(%struct.ST) align 4 %s) {
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; CHECK-LABEL: tc41:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: srawi 3, 3, 24
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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%shr = ashr i32 %0, 24
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ret i32 %shr
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}
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; Function Attrs: nounwind
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define i32 @tc42(ptr noundef byval(%struct.ST) align 4 %s) {
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; CHECK-LABEL: tc42:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: srawi 3, 3, 16
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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%shr = ashr i32 %0, 16
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ret i32 %shr
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}
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; Function Attrs: nounwind
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define i32 @tc43(ptr noundef byval(%struct.ST) align 4 %s) {
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; CHECK-LABEL: tc43:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: srawi 3, 3, 8
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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%shr = ashr i32 %0, 8
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ret i32 %shr
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}
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; Function Attrs: nounwind
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define i32 @utc44(ptr noundef byval(%struct.UST) align 4 %s) {
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; CHECK-LABEL: utc44:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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ret i32 %0
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}
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; Function Attrs: nounwind
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define i32 @utc41(ptr noundef byval(%struct.UST) align 4 %s) {
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; CHECK-LABEL: utc41:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: srwi 3, 3, 24
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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%shr = lshr i32 %0, 24
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ret i32 %shr
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}
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; Function Attrs: nounwind
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define i32 @utc42(ptr noundef byval(%struct.UST) align 4 %s) {
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; CHECK-LABEL: utc42:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: srwi 3, 3, 16
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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%shr = lshr i32 %0, 16
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ret i32 %shr
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}
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; Function Attrs: nounwind
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define i32 @utc43(ptr noundef byval(%struct.UST) align 4 %s) {
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; CHECK-LABEL: utc43:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stw 3, 24(1)
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; CHECK-NEXT: srwi 3, 3, 8
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; CHECK-NEXT: stw 4, 28(1)
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; CHECK-NEXT: blr
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entry:
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%0 = load i32, ptr %s, align 4
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%shr = lshr i32 %0, 8
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ret i32 %shr
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}
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