cbdccb30c2
If a virtual register is not assigned preferred physical register, it means some COPY instructions will be changed to real register move instructions. In this case we can try to split the virtual register in colder blocks, if success, the original COPY instructions can be deleted, and the new COPY instructions in colder blocks will be generated as register move instructions. It results in fewer dynamic register move instructions executed. The new test case split-reg-with-hint.ll gives an example, the hot path contains 24 instructions without this patch, now it is only 4 instructions with this patch. Differential Revision: https://reviews.llvm.org/D156491
226 lines
6.1 KiB
LLVM
226 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -O2 -o - %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-grtev4-linux-gnu"
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; Intended layout:
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; The code for tail-duplication during layout will produce the layout:
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; test1
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; test2
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; body1 (with copy of test2)
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; body2
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; exit
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define void @tail_dup_break_cfg(i32 %tag) {
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; CHECK-LABEL: tail_dup_break_cfg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: std 0, 64(1)
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; CHECK-NEXT: andi. 3, 30, 1
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; CHECK-NEXT: bc 12, 1, .LBB0_3
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; CHECK-NEXT: # %bb.1: # %test2
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; CHECK-NEXT: andi. 3, 30, 2
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; CHECK-NEXT: bne 0, .LBB0_4
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; CHECK-NEXT: .LBB0_2: # %exit
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB0_3: # %body1
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: andi. 3, 30, 2
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; CHECK-NEXT: beq 0, .LBB0_2
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; CHECK-NEXT: .LBB0_4: # %body2
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: b .LBB0_2
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entry:
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br label %test1
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test1:
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%tagbit1 = and i32 %tag, 1
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%tagbit1eq0 = icmp eq i32 %tagbit1, 0
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br i1 %tagbit1eq0, label %test2, label %body1, !prof !1 ; %test2 more likely
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body1:
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call void @a()
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call void @a()
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call void @a()
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call void @a()
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br label %test2
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test2:
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%tagbit2 = and i32 %tag, 2
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%tagbit2eq0 = icmp eq i32 %tagbit2, 0
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br i1 %tagbit2eq0, label %exit, label %body2, !prof !1 ; %exit more likely
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body2:
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call void @b()
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call void @b()
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call void @b()
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call void @b()
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br label %exit
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exit:
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ret void
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}
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; The branch weights here hint that we shouldn't tail duplicate in this case.
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define void @tail_dup_dont_break_cfg(i32 %tag) {
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; CHECK-LABEL: tail_dup_dont_break_cfg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: std 0, 64(1)
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; CHECK-NEXT: andi. 3, 30, 1
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; CHECK-NEXT: bc 4, 1, .LBB1_2
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; CHECK-NEXT: # %bb.1: # %body1
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl a
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB1_2: # %test2
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; CHECK-NEXT: andi. 3, 30, 2
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; CHECK-NEXT: beq 0, .LBB1_4
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; CHECK-NEXT: # %bb.3: # %body2
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl b
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB1_4: # %exit
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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br label %test1
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test1:
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%tagbit1 = and i32 %tag, 1
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%tagbit1eq0 = icmp eq i32 %tagbit1, 0
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br i1 %tagbit1eq0, label %test2, label %body1, !prof !1 ; %test2 more likely
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body1:
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call void @a()
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call void @a()
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call void @a()
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call void @a()
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br label %test2
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test2:
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%tagbit2 = and i32 %tag, 2
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%tagbit2eq0 = icmp ne i32 %tagbit2, 0
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br i1 %tagbit2eq0, label %body2, label %exit, !prof !3 ; %body2 more likely
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body2:
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call void @b()
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call void @b()
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call void @b()
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call void @b()
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br label %exit
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exit:
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ret void
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}
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declare void @a()
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declare void @b()
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declare void @c()
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declare void @d()
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; This function arranges for the successors of %succ to have already been laid
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; out. When we consider whether to lay out succ after bb and to tail-duplicate
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; it, v and ret have already been placed, so we tail-duplicate as it removes a
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; branch and strictly increases fallthrough
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define void @tail_dup_no_succ(i32 %tag) {
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; CHECK-LABEL: tail_dup_no_succ:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
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; CHECK-NEXT: stdu 1, -48(1)
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; CHECK-NEXT: andi. 4, 3, 1
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; CHECK-NEXT: std 0, 64(1)
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; CHECK-NEXT: bc 12, 1, .LBB2_3
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; CHECK-NEXT: .LBB2_1: # %v
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; CHECK-NEXT: bl d
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl d
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB2_2: # %ret
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB2_3: # %bb
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; CHECK-NEXT: andi. 4, 3, 2
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; CHECK-NEXT: bne 0, .LBB2_5
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; CHECK-NEXT: # %bb.4: # %succ
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; CHECK-NEXT: andi. 3, 3, 4
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; CHECK-NEXT: beq 0, .LBB2_2
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; CHECK-NEXT: b .LBB2_1
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; CHECK-NEXT: .LBB2_5: # %c
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; CHECK-NEXT: mr 30, 3
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; CHECK-NEXT: bl c
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl c
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; CHECK-NEXT: nop
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; CHECK-NEXT: mr 3, 30
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; CHECK-NEXT: andi. 3, 3, 4
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; CHECK-NEXT: beq 0, .LBB2_2
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; CHECK-NEXT: b .LBB2_1
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entry:
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%tagbit1 = and i32 %tag, 1
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%tagbit1eq0 = icmp eq i32 %tagbit1, 0
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br i1 %tagbit1eq0, label %v, label %bb, !prof !2 ; %v very much more likely
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bb:
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%tagbit2 = and i32 %tag, 2
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%tagbit2eq0 = icmp eq i32 %tagbit2, 0
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br i1 %tagbit2eq0, label %succ, label %c, !prof !3 ; %succ more likely
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c:
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call void @c()
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call void @c()
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br label %succ
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succ:
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%tagbit3 = and i32 %tag, 4
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%tagbit3eq0 = icmp eq i32 %tagbit3, 0
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br i1 %tagbit3eq0, label %ret, label %v, !prof !1 ; %u more likely
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v:
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call void @d()
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call void @d()
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br label %ret
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ret:
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ret void
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}
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!1 = !{!"branch_weights", i32 5, i32 3}
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!2 = !{!"branch_weights", i32 95, i32 5}
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!3 = !{!"branch_weights", i32 8, i32 3}
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