26ba186bd0
There are no partial vector loads on pwr7 so current v4i8 codegen is an int load then store to vector sized temp and re-load as vector. Try to use lfiwax to load 32 bits into an FP reg and take advantage of VSX FP and vector reg sharing to move the result to the right vector position.
278 lines
10 KiB
LLVM
278 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-LE-P9
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
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; xscvdpsxws and xscvdpsxws is only available on Power7 and above
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; Codgen is different for Power7, Power8, and Power9.
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define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
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; CHECK-LE-P7-LABEL: test:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI0_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI0_0@toc@l
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
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; CHECK-LE-P7-NEXT: xxswapd v3, vs0
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; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-LE-P8-NEXT: xscvdpsxws v4, f1
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
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; CHECK-LE-P8-NEXT: xxswapd v3, vs0
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3
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; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1
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; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-BE-P8-NEXT: xscvdpsxws v4, f1
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; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3
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; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
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; CHECK-BE-P9-NEXT: blr
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entry:
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%conv = fptosi double %b to i32
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%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
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ret <4 x i32> %vecins
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}
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define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
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; CHECK-LE-P7-LABEL: test2:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI1_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI1_0@toc@l
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
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; CHECK-LE-P7-NEXT: xxswapd v3, vs0
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; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test2:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-LE-P8-NEXT: xscvdpsxws v4, f1
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
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; CHECK-LE-P8-NEXT: xxswapd v3, vs0
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test2:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test2:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3
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; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1
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; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test2:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-BE-P8-NEXT: xscvdpsxws v4, f1
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; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3
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; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test2:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
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; CHECK-BE-P9-NEXT: blr
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entry:
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%conv = fptosi float %b to i32
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%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
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ret <4 x i32> %vecins
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}
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define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
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; CHECK-LE-P7-LABEL: test3:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI2_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI2_0@toc@l
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
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; CHECK-LE-P7-NEXT: xxswapd v3, vs0
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; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test3:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-LE-P8-NEXT: xscvdpuxws v4, f1
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l
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; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
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; CHECK-LE-P8-NEXT: xxswapd v3, vs0
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test3:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test3:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l
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; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3
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; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1
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; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test3:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-BE-P8-NEXT: xscvdpuxws v4, f1
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; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l
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; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3
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; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test3:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
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; CHECK-BE-P9-NEXT: blr
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entry:
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%conv = fptoui double %b to i32
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%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
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ret <4 x i32> %vecins
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}
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define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
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; CHECK-LE-P7-LABEL: test4:
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; CHECK-LE-P7: # %bb.0: # %entry
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; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P7-NEXT: addi r3, r1, -4
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; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI3_0@toc@ha
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; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI3_0@toc@l
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; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4
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; CHECK-LE-P7-NEXT: xxswapd v3, vs0
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; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1
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; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P7-NEXT: blr
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;
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; CHECK-LE-P8-LABEL: test4:
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; CHECK-LE-P8: # %bb.0: # %entry
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; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
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; CHECK-LE-P8-NEXT: xscvdpuxws v4, f1
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; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
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; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3
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; CHECK-LE-P8-NEXT: xxswapd v3, vs0
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; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3
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; CHECK-LE-P8-NEXT: blr
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;
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; CHECK-LE-P9-LABEL: test4:
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; CHECK-LE-P9: # %bb.0: # %entry
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; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0
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; CHECK-LE-P9-NEXT: blr
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;
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; CHECK-BE-P7-LABEL: test4:
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; CHECK-BE-P7: # %bb.0: # %entry
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; CHECK-BE-P7-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P7-NEXT: addi r3, r1, -4
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; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3
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; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3
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; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI3_0@toc@ha
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; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI3_0@toc@l
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; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3
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; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1
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; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4
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; CHECK-BE-P7-NEXT: blr
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;
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; CHECK-BE-P8-LABEL: test4:
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; CHECK-BE-P8: # %bb.0: # %entry
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; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha
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; CHECK-BE-P8-NEXT: xscvdpuxws v4, f1
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; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l
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; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3
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; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3
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; CHECK-BE-P8-NEXT: blr
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;
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; CHECK-BE-P9-LABEL: test4:
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; CHECK-BE-P9: # %bb.0: # %entry
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; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1
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; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12
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; CHECK-BE-P9-NEXT: blr
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entry:
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%conv = fptoui float %b to i32
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%vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
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ret <4 x i32> %vecins
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}
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