5403c59c60
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
110 lines
3.4 KiB
LLVM
110 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s
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; ISEL matches address mode xaddr.
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define i8 @test_xaddr(ptr %p) {
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; CHECK-LABEL: test_xaddr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r4, 0
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: ori r4, r4, 40000
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; CHECK-NEXT: lbzx r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%p.addr = alloca ptr, align 8
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store ptr %p, ptr %p.addr, align 8
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%0 = load ptr, ptr %p.addr, align 8
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%add.ptr = getelementptr inbounds i8, ptr %0, i64 40000
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%1 = load i8, ptr %add.ptr, align 1
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ret i8 %1
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}
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; ISEL matches address mode xaddrX4.
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define i64 @test_xaddrX4(ptr %p) {
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; CHECK-LABEL: test_xaddrX4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r4, 3
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; CHECK-NEXT: std r3, -8(r1)
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; CHECK-NEXT: ldx r3, r3, r4
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; CHECK-NEXT: blr
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entry:
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%p.addr = alloca ptr, align 8
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store ptr %p, ptr %p.addr, align 8
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%0 = load ptr, ptr %p.addr, align 8
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%add.ptr = getelementptr inbounds i8, ptr %0, i64 3
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%1 = load i64, ptr %add.ptr, align 8
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ret i64 %1
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}
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; ISEL matches address mode xaddrX16.
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define <2 x double> @test_xaddrX16(ptr %arr) {
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; CHECK-LABEL: test_xaddrX16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r4, 40
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; CHECK-NEXT: lxvx vs34, r3, r4
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; CHECK-NEXT: blr
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entry:
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%arrayidx1 = getelementptr inbounds double, ptr %arr, i64 5
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%0 = load <2 x double>, ptr %arrayidx1, align 16
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ret <2 x double> %0
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}
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; ISEL matches address mode xoaddr.
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define void @test_xoaddr(ptr %arr, ptr %arrTo) {
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; CHECK-LABEL: test_xoaddr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r5, 8
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; CHECK-NEXT: lxvx vs0, r3, r5
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: stxvx vs0, r4, r3
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; CHECK-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i32, ptr %arrTo, i64 1
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%arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2
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%0 = load <4 x i32>, ptr %arrayidx1, align 8
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store <4 x i32> %0, ptr %arrayidx, align 8
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ret void
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}
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; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
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; loop.
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define i64 @test_xaddrX4_loop(ptr %p) {
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; CHECK-LABEL: test_xaddrX4_loop:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi r4, r3, -8
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; CHECK-NEXT: li r3, 8
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; CHECK-NEXT: li r5, 3
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; CHECK-NEXT: mtctr r3
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB4_1: # %for.body
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; CHECK-NEXT: #
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; CHECK-NEXT: ldu r6, 8(r4)
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; CHECK-NEXT: ldx r7, r4, r5
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; CHECK-NEXT: maddld r3, r7, r6, r3
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; CHECK-NEXT: bdnz .LBB4_1
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; CHECK-NEXT: # %bb.2: # %for.end
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; CHECK-NEXT: blr
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; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.015 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
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%res.014 = phi i64 [ 0, %entry ], [ %add, %for.body ]
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%mul = shl i64 %i.015, 3
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%add.ptr = getelementptr inbounds i8, ptr %p, i64 %mul
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%0 = load i64, ptr %add.ptr, align 8
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%add.ptr3 = getelementptr inbounds i8, ptr %add.ptr, i64 3
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%1 = load i64, ptr %add.ptr3, align 8
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%mul4 = mul i64 %1, %0
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%add = add i64 %mul4, %res.014
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%inc = add nuw nsw i64 %i.015, 1
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%exitcond = icmp eq i64 %inc, 8
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret i64 %add
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}
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