53c37f300d
On PowerPC there are 128 bit VSX registers. These registers are half overlapped with 64 bit floating point registers (FPR). The 64 bit half of the VXS register that does not overlap with the FPR does not overlap with any other register class. The FPR are the only subregisters of the VSX registers but they do not fully cover the 128 bit super register. This leads to incorrect lane masks being created. This patch adds phony registers for the other half of the VSX registers in order to fully cover them and to make sure that the lane masks are not the same for the VSX and the floating point register.
148 lines
4.3 KiB
LLVM
148 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-late-peephole=true < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-BE
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P7
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @geti(<4 x i32> %a, i32 zeroext %b) {
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; CHECK-LABEL: geti:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 2
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; CHECK-NEXT: andc 3, 3, 5
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; CHECK-NEXT: sldi 3, 3, 2
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; CHECK-NEXT: lvsl 3, 0, 3
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: sldi 3, 3, 5
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; CHECK-NEXT: vperm 2, 2, 2, 3
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; CHECK-NEXT: mfvsrd 4, 34
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; CHECK-NEXT: srd 3, 4, 3
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: geti:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: andi. 3, 5, 2
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; CHECK-BE-NEXT: sldi 3, 3, 2
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; CHECK-BE-NEXT: lvsl 3, 0, 3
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; CHECK-BE-NEXT: li 3, 1
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; CHECK-BE-NEXT: andc 3, 3, 5
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; CHECK-BE-NEXT: sldi 3, 3, 5
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; CHECK-BE-NEXT: vperm 2, 2, 2, 3
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; CHECK-BE-NEXT: mfvsrd 4, 34
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; CHECK-BE-NEXT: srd 3, 4, 3
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; CHECK-BE-NEXT: clrldi 3, 3, 32
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; CHECK-BE-NEXT: blr
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;
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; CHECK-P7-LABEL: geti:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: addi 4, 1, -16
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; CHECK-P7-NEXT: rlwinm 3, 5, 2, 28, 29
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; CHECK-P7-NEXT: stxvw4x 34, 0, 4
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; CHECK-P7-NEXT: lwzx 3, 4, 3
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; CHECK-P7-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %b
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ret i32 %vecext
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @getl(<2 x i64> %a, i32 zeroext %b) {
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; CHECK-LABEL: getl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: andc 3, 3, 5
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; CHECK-NEXT: sldi 3, 3, 3
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; CHECK-NEXT: lvsl 3, 0, 3
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; CHECK-NEXT: vperm 2, 2, 2, 3
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; CHECK-NEXT: mfvsrd 3, 34
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: getl:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: andi. 3, 5, 1
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; CHECK-BE-NEXT: sldi 3, 3, 3
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; CHECK-BE-NEXT: lvsl 3, 0, 3
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; CHECK-BE-NEXT: vperm 2, 2, 2, 3
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; CHECK-BE-NEXT: mfvsrd 3, 34
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; CHECK-BE-NEXT: blr
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;
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; CHECK-P7-LABEL: getl:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: addi 4, 1, -16
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; CHECK-P7-NEXT: rlwinm 3, 5, 3, 28, 28
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; CHECK-P7-NEXT: stxvd2x 34, 0, 4
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; CHECK-P7-NEXT: ldx 3, 4, 3
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; CHECK-P7-NEXT: blr
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entry:
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%vecext = extractelement <2 x i64> %a, i32 %b
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ret i64 %vecext
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}
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; Function Attrs: norecurse nounwind readnone
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define float @getf(<4 x float> %a, i32 zeroext %b) {
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; CHECK-LABEL: getf:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xori 3, 5, 3
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; CHECK-NEXT: sldi 3, 3, 2
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; CHECK-NEXT: lvsl 3, 0, 3
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; CHECK-NEXT: vperm 2, 2, 2, 3
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; CHECK-NEXT: xscvspdpn 1, 34
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: getf:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: sldi 3, 5, 2
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; CHECK-BE-NEXT: lvsl 3, 0, 3
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; CHECK-BE-NEXT: vperm 2, 2, 2, 3
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; CHECK-BE-NEXT: xscvspdpn 1, 34
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; CHECK-BE-NEXT: blr
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;
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; CHECK-P7-LABEL: getf:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: addi 4, 1, -16
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; CHECK-P7-NEXT: rlwinm 3, 5, 2, 28, 29
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; CHECK-P7-NEXT: stxvw4x 34, 0, 4
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; CHECK-P7-NEXT: lfsx 1, 4, 3
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; CHECK-P7-NEXT: blr
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entry:
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%vecext = extractelement <4 x float> %a, i32 %b
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ret float %vecext
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}
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; Function Attrs: norecurse nounwind readnone
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define double @getd(<2 x double> %a, i32 zeroext %b) {
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; CHECK-LABEL: getd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: andc 3, 3, 5
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; CHECK-NEXT: sldi 3, 3, 3
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; CHECK-NEXT: lvsl 3, 0, 3
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; CHECK-NEXT: vperm 2, 2, 2, 3
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; CHECK-NEXT: xxlor 1, 34, 34
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: getd:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: andi. 3, 5, 1
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; CHECK-BE-NEXT: sldi 3, 3, 3
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; CHECK-BE-NEXT: lvsl 3, 0, 3
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; CHECK-BE-NEXT: vperm 2, 2, 2, 3
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; CHECK-BE-NEXT: xxlor 1, 34, 34
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; CHECK-BE-NEXT: blr
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;
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; CHECK-P7-LABEL: getd:
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; CHECK-P7: # %bb.0: # %entry
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; CHECK-P7-NEXT: andi. 3, 5, 1
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; CHECK-P7-NEXT: sldi 3, 3, 3
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; CHECK-P7-NEXT: lvsl 3, 0, 3
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; CHECK-P7-NEXT: vperm 2, 2, 2, 3
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; CHECK-P7-NEXT: xxlor 1, 34, 34
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; CHECK-P7-NEXT: blr
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entry:
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%vecext = extractelement <2 x double> %a, i32 %b
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ret double %vecext
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}
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