9fc347aa4e
PromoteIntRes_BUILD_VECTOR currently always ANY_EXTENDs build vector operands, but if this is a constant boolean vector we're losing the useful ability to keep the vector matching the BooleanContents mode used by the target. This patch extends constant boolean vectors according to target BooleanContents, allowing a number of additional all-bits folds (notable XOR -> NOT conversions) to occur. Differential Revision: https://reviews.llvm.org/D129641
69 lines
2.3 KiB
LLVM
69 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
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define dso_local <4 x i32> @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsel vs34, vs34, vs35, vs36
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; CHECK-NEXT: blr
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entry:
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%neg.i = xor <4 x i32> %c, <i32 -1, i32 -1, i32 -1, i32 -1>
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%and.i = and <4 x i32> %neg.i, %a
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%and1.i = and <4 x i32> %c, %b
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%or.i = or <4 x i32> %and1.i, %and.i
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ret <4 x i32> %or.i
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}
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define dso_local <8 x i16> @test2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsel vs34, vs34, vs35, vs36
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; CHECK-NEXT: blr
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entry:
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%neg.i = xor <8 x i16> %c, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%and.i = and <8 x i16> %a, %neg.i
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%and1.i = and <8 x i16> %c, %b
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%or.i = or <8 x i16> %and.i, %and1.i
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ret <8 x i16> %or.i
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}
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define dso_local <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsel vs34, vs34, vs35, vs36
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; CHECK-NEXT: blr
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entry:
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%neg.i = xor <16 x i8> %c, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%and.i = and <16 x i8> %neg.i, %a
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%and1.i = and <16 x i8> %c, %b
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%or.i = or <16 x i8> %and.i, %and1.i
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ret <16 x i8> %or.i
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}
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define dso_local <2 x i64> @test4(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsel vs34, vs34, vs35, vs36
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; CHECK-NEXT: blr
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entry:
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%neg.i = xor <2 x i64> %c, <i64 -1, i64 -1>
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%and.i = and <2 x i64> %a, %neg.i
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%and1.i = and <2 x i64> %c, %b
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%or.i = or <2 x i64> %and.i, %and1.i
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ret <2 x i64> %or.i
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}
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; vXi1 constants are sign-extended to preserve XXSEL pattern.
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define dso_local <4 x i1> @test5(<4 x i1> %a, <4 x i1> %b, <4 x i1> %c) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsel vs34, vs34, vs35, vs36
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; CHECK-NEXT: blr
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entry:
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%neg.i = xor <4 x i1> %c, <i1 -1, i1 -1, i1 -1, i1 -1>
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%and.i = and <4 x i1> %a, %neg.i
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%and1.i = and <4 x i1> %c, %b
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%or.i = or <4 x i1> %and.i, %and1.i
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ret <4 x i1> %or.i
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}
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