c2e7c9cb33
In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`. This is because IRTranslator uses SExt for indices. In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt. This change includes both documentation, SelectionDAG and IRTranslator. We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86 This patch fixes issue #57452. Differential Revision: https://reviews.llvm.org/D132978
273 lines
8.0 KiB
LLVM
273 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
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define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {
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; CHECK-LE-LABEL: test_add1:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: clrldi 3, 5, 32
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; CHECK-LE-NEXT: vextubrx 3, 3, 2
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: clrldi 3, 3, 56
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: clrldi 3, 5, 32
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; CHECK-BE-NEXT: vextublx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 6
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; CHECK-BE-NEXT: clrldi 3, 3, 56
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 %index
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%conv = zext i8 %vecext to i32
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%conv1 = zext i8 %c to i32
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%add = add nuw nsw i32 %conv, %conv1
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%conv2 = trunc i32 %add to i8
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ret i8 %conv2
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}
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define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) {
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; CHECK-LE-LABEL: test_add2:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: clrldi 3, 5, 32
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; CHECK-LE-NEXT: vextubrx 3, 3, 2
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: extsb 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: clrldi 3, 5, 32
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; CHECK-BE-NEXT: vextublx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 6
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; CHECK-BE-NEXT: extsb 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <16 x i8> %a, i32 %index
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%conv3 = zext i8 %vecext to i32
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%conv14 = zext i8 %c to i32
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%add = add nuw nsw i32 %conv3, %conv14
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%conv2 = trunc i32 %add to i8
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ret i8 %conv2
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}
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define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) {
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; CHECK-LE-LABEL: test_add3:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: clrldi 3, 5, 32
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; CHECK-LE-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: clrldi 3, 3, 48
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add3:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: clrldi 3, 5, 32
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; CHECK-BE-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-BE-NEXT: vextuhlx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 6
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; CHECK-BE-NEXT: clrldi 3, 3, 48
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 %index
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%conv = zext i16 %vecext to i32
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%conv1 = zext i16 %c to i32
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%add = add nuw nsw i32 %conv, %conv1
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%conv2 = trunc i32 %add to i16
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ret i16 %conv2
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}
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define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) {
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; CHECK-LE-LABEL: test_add4:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: clrldi 3, 5, 32
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; CHECK-LE-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: extsh 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add4:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: clrldi 3, 5, 32
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; CHECK-BE-NEXT: rlwinm 3, 3, 1, 28, 30
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; CHECK-BE-NEXT: vextuhlx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 6
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; CHECK-BE-NEXT: extsh 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %a, i32 %index
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%conv5 = zext i16 %vecext to i32
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%conv16 = zext i16 %c to i32
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%add = add nuw nsw i32 %conv5, %conv16
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%conv2 = trunc i32 %add to i16
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ret i16 %conv2
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}
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define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) {
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; CHECK-LE-LABEL: test_add5:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: clrldi 3, 5, 32
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; CHECK-LE-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: clrldi 3, 3, 32
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add5:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: clrldi 3, 5, 32
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; CHECK-BE-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 6
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; CHECK-BE-NEXT: clrldi 3, 3, 32
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %index
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%add = add i32 %vecext, %c
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ret i32 %add
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}
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define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) {
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; CHECK-LE-LABEL: test_add6:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: clrldi 3, 5, 32
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; CHECK-LE-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add6:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: clrldi 3, 5, 32
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; CHECK-BE-NEXT: rlwinm 3, 3, 2, 28, 29
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 6
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; CHECK-BE-NEXT: extsw 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %index
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%add = add nsw i32 %vecext, %c
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ret i32 %add
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}
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; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx
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define zeroext i32 @test7(<4 x i32> %a) {
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; CHECK-LE-LABEL: test7:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mfvsrwz 3, 34
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test7:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 2
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ret i32 %vecext
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}
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define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) {
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; CHECK-LE-LABEL: testadd_7:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mfvsrwz 3, 34
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; CHECK-LE-NEXT: add 3, 3, 5
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; CHECK-LE-NEXT: clrldi 3, 3, 32
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: testadd_7:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 5
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; CHECK-BE-NEXT: clrldi 3, 3, 32
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 2
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%add = add i32 %vecext, %c
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ret i32 %add
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}
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define signext i32 @test8(<4 x i32> %a) {
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; CHECK-LE-LABEL: test8:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mfvsrwz 3, 34
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: extsw 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 2
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ret i32 %vecext
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}
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define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) {
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; CHECK-LE-LABEL: testadd_8:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mfvsrwz 3, 34
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; CHECK-LE-NEXT: add 3, 3, 5
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: testadd_8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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; CHECK-BE-NEXT: vextuwlx 3, 3, 2
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; CHECK-BE-NEXT: add 3, 3, 5
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; CHECK-BE-NEXT: extsw 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 2
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%add = add nsw i32 %vecext, %c
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ret i32 %add
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}
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; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx
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define signext i32 @test9(<4 x i32> %a) {
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; CHECK-LE-LABEL: test9:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: li 3, 4
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test9:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mfvsrwz 3, 34
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; CHECK-BE-NEXT: extsw 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 1
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ret i32 %vecext
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}
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define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) {
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; CHECK-LE-LABEL: testadd_9:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: li 3, 4
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: add 3, 3, 5
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: testadd_9:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mfvsrwz 3, 34
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; CHECK-BE-NEXT: add 3, 3, 5
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; CHECK-BE-NEXT: extsw 3, 3
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %a, i32 1
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%add = add nsw i32 %vecext, %c
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ret i32 %add
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}
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