Wang Pengcheng 08165c444e
[RISCV] Add searchable table for tune information (#66193)
There are many information that can be used for tuning, like
alignments, cache line size, etc. But we can't make all of them
`SubtargetFeature` because some of them are not with enumerable
value, for example, `PrefetchDistance` used by `LoopDataPrefetch`.

In this patch, a searchable table `RISCVTuneInfoTable` is added,
in which each entry contains the CPU name and all tune information
defined in `RISCVTuneInfo`. Each field of `RISCVTuneInfo` should
have a default value and processor definitions can override the
default value via `let` statements.

We don't need to define a `RISCVTuneInfo` for each processor and
it will use the default value (which is for `generic`) if no
`RISCVTuneInfo` defined.

For processors in the same series, a subclass can inherit from
`RISCVTuneInfo` and override the fields. And we can also override
the fields in processor definitions if there are some differences
in the same processor series.

When initilizing `RISCVSubtarget`, we will use `TuneCPU` as the
key to serach the tune info table. So, the behavior here is if
we don't specify the tune CPU, we will use specified `CPU`, which
is expected I think. 

This patch almost undoes 61ab106, in which I added tune features
of preferred function/loop alignments. More tune information can
be added in the future.
2023-09-26 12:26:35 +08:00

45 lines
1.2 KiB
LLVM

; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16
; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileCheck %s -check-prefix=ALIGN_32
declare void @foo()
define void @test(i32 %n, i32 %m) nounwind {
; CHECK-LABEL: test:
; CHECK-NOT: .p2align
; CHECK: ret
; ALIGN_16-LABEL: test:
; ALIGN_16: .p2align 4{{$}}
; ALIGN_16-NEXT: .LBB0_1: # %outer
; ALIGN_16: .p2align 4{{$}}
; ALIGN_16-NEXT: .LBB0_2: # %inner
; ALIGN_32-LABEL: test:
; ALIGN_32: .p2align 5{{$}}
; ALIGN_32-NEXT: .LBB0_1: # %outer
; ALIGN_32: .p2align 5{{$}}
; ALIGN_32-NEXT: .LBB0_2: # %inner
entry:
br label %outer
outer:
%outer.iv = phi i32 [0, %entry], [%outer.iv.next, %outer_bb]
br label %inner
inner:
%inner.iv = phi i32 [0, %outer], [%inner.iv.next, %inner]
call void @foo()
%inner.iv.next = add i32 %inner.iv, 1
%inner.cond = icmp ne i32 %inner.iv.next, %m
br i1 %inner.cond, label %inner, label %outer_bb
outer_bb:
%outer.iv.next = add i32 %outer.iv, 1
%outer.cond = icmp ne i32 %outer.iv.next, %n
br i1 %outer.cond, label %outer, label %exit
exit:
ret void
}