e722d9662d
Fixes https://github.com/llvm/llvm-project/issues/80744. This transform doesn't handled vectors at all, The fixed length ones pass the first check, but would fail the constant operand checks which immediate follow. This patch takes the simplest approach, and just guards the transform for scalar integers.
80 lines
2.5 KiB
LLVM
80 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+v < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+v < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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define i32 @and_add_lsr(i32 %x, i32 %y) {
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; RV32I-LABEL: and_add_lsr:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: srli a1, a1, 20
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; RV32I-NEXT: and a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_add_lsr:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addiw a0, a0, -1
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; RV64I-NEXT: srliw a1, a1, 20
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; RV64I-NEXT: and a0, a1, a0
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; RV64I-NEXT: ret
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%1 = add i32 %x, 4095
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%2 = lshr i32 %y, 20
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%r = and i32 %2, %1
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ret i32 %r
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}
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; Make sure we don't crash on fixed length vectors
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define <2 x i32> @and_add_lsr_vec(<2 x i32> %x, <2 x i32> %y) {
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; RV32I-LABEL: and_add_lsr_vec:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; RV32I-NEXT: vadd.vx v8, v8, a0
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; RV32I-NEXT: vsrl.vi v9, v9, 20
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; RV32I-NEXT: vand.vv v8, v9, v8
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_add_lsr_vec:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; RV64I-NEXT: vadd.vx v8, v8, a0
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; RV64I-NEXT: vsrl.vi v9, v9, 20
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; RV64I-NEXT: vand.vv v8, v9, v8
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; RV64I-NEXT: ret
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%1 = add <2 x i32> %x, splat (i32 4095)
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%2 = lshr <2 x i32> %y, splat (i32 20)
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%r = and <2 x i32> %2, %1
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ret <2 x i32> %r
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}
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; Make sure we don't crash on scalable vectors
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define <vscale x 2 x i32> @and_add_lsr_vec2(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
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; RV32I-LABEL: and_add_lsr_vec2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; RV32I-NEXT: vadd.vx v8, v8, a0
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; RV32I-NEXT: vsrl.vi v9, v9, 20
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; RV32I-NEXT: vand.vv v8, v9, v8
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_add_lsr_vec2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; RV64I-NEXT: vadd.vx v8, v8, a0
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; RV64I-NEXT: vsrl.vi v9, v9, 20
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; RV64I-NEXT: vand.vv v8, v9, v8
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; RV64I-NEXT: ret
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%1 = add <vscale x 2 x i32> %x, splat (i32 4095)
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%2 = lshr <vscale x 2 x i32> %y, splat (i32 20)
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%r = and <vscale x 2 x i32> %2, %1
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ret <vscale x 2 x i32> %r
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}
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