4e115b7d88
Clang computes the default ABI if -mabi is empty and encode it in LLVM IR module flag since D105555. For correctness, llc need to give the same target-abi (Options.MCOptions.ABIName) with ABI encoded in IR. The getSubtargetImpl already has a check for them only if Options.MCOptions.ABIName is not empty. In order to get more robustness we could have a check for explicit ABI, but now we have two different logic to compute the default ABI. The front-end ABI is defautl to the ilp32/ilp32e/lp64, and ilp32d/lp64d when hardware support for extension D. The backend ABI is default to the ilp32/ilp32e/lp64. Reviewed by: asb, jrtc27 Differential Revision: https://reviews.llvm.org/D118333
62 lines
2.4 KiB
LLVM
62 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32ID %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64ID %s
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define void @testcase() nounwind {
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; RV32I-LABEL: testcase:
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; RV32I: sw s1, {{[0-9]+}}(sp)
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; RV32I-NEXT: sw s2, {{[0-9]+}}(sp)
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; RV32I-NOT: fsw fs0, {{[0-9]+}}(sp)
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; RV32I-NOT: fsd fs0, {{[0-9]+}}(sp)
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;
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; RV64I-LABEL: testcase:
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; RV64I: sd s1, {{[0-9]+}}(sp)
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; RV64I-NEXT: sd s2, {{[0-9]+}}(sp)
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; RV64I-NOT: fsw fs0, {{[0-9]+}}(sp)
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; RV64I-NOT: fsd fs0, {{[0-9]+}}(sp)
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;
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; RV32IF-LABEL: testcase:
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; RV32IF: sw s1, {{[0-9]+}}(sp)
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; RV32IF-NEXT: sw s2, {{[0-9]+}}(sp)
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; RV32IF-NEXT: fsw fs0, {{[0-9]+}}(sp)
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; RV32IF-NEXT: fsw fs1, {{[0-9]+}}(sp)
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;
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; RV64IF-LABEL: testcase:
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; RV64IF: sd s1, {{[0-9]+}}(sp)
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; RV64IF-NEXT: sd s2, {{[0-9]+}}(sp)
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; RV64IF-NEXT: fsw fs0, {{[0-9]+}}(sp)
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; RV64IF-NEXT: fsw fs1, {{[0-9]+}}(sp)
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;
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; RV32ID-LABEL: testcase:
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; RV32ID: sw s1, {{[0-9]+}}(sp)
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; RV32ID-NEXT: sw s2, {{[0-9]+}}(sp)
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; RV32ID-NEXT: fsd fs0, {{[0-9]+}}(sp)
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; RV32ID-NEXT: fsd fs1, {{[0-9]+}}(sp)
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;
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; RV64ID-LABEL: testcase:
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; RV64ID: sd s1, {{[0-9]+}}(sp)
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; RV64ID-NEXT: sd s2, {{[0-9]+}}(sp)
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; RV64ID-NEXT: fsd fs0, {{[0-9]+}}(sp)
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; RV64ID-NEXT: fsd fs1, {{[0-9]+}}(sp)
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tail call void asm sideeffect "", "~{f8},~{f9},~{x9},~{x18}"()
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ret void
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}
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