b8ed69ecc0
This intrinsic was introduced by #81331, which is a lot like `llvm.readcyclecounter`. For the RISCV implementation, we rename `ReadCycleWide` pseudo to `ReadCounterWide` and make it accept two operands (the low and high parts of the counter). As for legalization and lowering parts, we reuse the code of `ISD::READCYCLECOUNTER` (make it able to handle both intrinsics), and we use `time` CSR for `ISD::READSTEADYCOUNTER`. Tests using Clang builtins are runned on real hardware and it works as excepted. Reviewers: asb, MaskRay, dtcxzyw, preames, topperc, jhuber6 Reviewed By: jhuber6, asb, MaskRay, dtcxzyw Pull Request: https://github.com/llvm/llvm-project/pull/82322
29 lines
916 B
LLVM
29 lines
916 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; Verify that we lower @llvm.readsteadycounter() correctly.
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declare i64 @llvm.readsteadycounter()
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define i64 @test_builtin_readsteadycounter() nounwind {
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; RV32I-LABEL: test_builtin_readsteadycounter:
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; RV32I: # %bb.0:
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; RV32I-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
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; RV32I-NEXT: rdtimeh a1
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; RV32I-NEXT: rdtime a0
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; RV32I-NEXT: rdtimeh a2
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; RV32I-NEXT: bne a1, a2, .LBB0_1
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; RV32I-NEXT: # %bb.2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_builtin_readsteadycounter:
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; RV64I: # %bb.0:
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; RV64I-NEXT: rdtime a0
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; RV64I-NEXT: ret
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%1 = tail call i64 @llvm.readsteadycounter()
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ret i64 %1
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}
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