3ac9fe69f7
This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register count to 16(x0-x16). * The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits. `RVE` can be combined with all current standard extensions. The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are: * Only 6 integer argument registers (rather than 8). * Only 2 callee-saved registers (rather than 12). * A Stack Alignment of 32bits (rather than 128bits). * ilp32e isn't compatible with D ISA extension. If `ilp32e` or `lp64` is used with an ISA that has any of the registers x16-x31 and f0-f31, then these registers are considered temporaries. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment\ to 4-bytes for types with length of 2*XLEN. FastCC is also supported on RVE, while GHC isn't since there is only one avaiable register. Differential Revision: https://reviews.llvm.org/D70401
26 lines
737 B
LLVM
26 lines
737 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=riscv32 -mattr=+e -verify-machineinstrs < %s \
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; RUN: | FileCheck %s
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; TODO: Add more tests.
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define i32 @exhausted(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
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; CHECK-LABEL: exhausted:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw t0, 0(sp)
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; CHECK-NEXT: add a0, a0, a1
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; CHECK-NEXT: add a2, a3, a2
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; CHECK-NEXT: add a0, a2, a0
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; CHECK-NEXT: add a4, a5, a4
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; CHECK-NEXT: add a0, a4, a0
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; CHECK-NEXT: add a0, t0, a0
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; CHECK-NEXT: ret
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%1 = add i32 %a, %b
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%2 = add i32 %c, %1
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%3 = add i32 %d, %2
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%4 = add i32 %e, %3
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%5 = add i32 %f, %4
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%6 = add i32 %g, %5
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ret i32 %6
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}
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