2817873082
This helps the 3 vendor extensions that make sext_inreg i1 legal. I'm delaying this until after LegalizeDAG since we normally have sext_inreg i1 up until LegalizeDAG turns it into and+neg. I also delayed the recently added (sext_inreg (xor (setcc), -1), i1) combine. Though the xor isn't likely to appear before LegalizeDAG anyway.
493 lines
11 KiB
LLVM
493 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
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; RUN: | FileCheck %s
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; NDS.BBC
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define i32 @bbc(i32 %a) nounwind {
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; CHECK-LABEL: bbc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bbc a0, 16, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %t
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_2: # %f
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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%and = and i32 %a, 65536
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%tst = icmp ne i32 %and, 0
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br i1 %tst, label %t, label %f
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define i32 @select_bbc(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: select_bbc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bbc a0, 16, .LBB1_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a1, a2
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: ret
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%and = and i32 %a, 65536
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%tst = icmp eq i32 %and, 0
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%ret = select i1 %tst, i32 %b, i32 %c
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ret i32 %ret
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}
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; NDS.BBS
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define i32 @bbs(i32 %a) nounwind {
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; CHECK-LABEL: bbs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bbs a0, 16, .LBB2_2
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; CHECK-NEXT: # %bb.1: # %t
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_2: # %f
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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%and = and i32 %a, 65536
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%tst = icmp eq i32 %and, 0
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br i1 %tst, label %t, label %f
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define i32 @select_bbs(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: select_bbs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bbs a0, 16, .LBB3_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a1, a2
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; CHECK-NEXT: .LBB3_2:
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: ret
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%and = and i32 %a, 65536
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%tst = icmp ne i32 %and, 0
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%ret = select i1 %tst, i32 %b, i32 %c
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ret i32 %ret
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}
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; NDS.BEQC
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define i32 @beqc(i32 %a) nounwind {
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; CHECK-LABEL: beqc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.beqc a0, 5, .LBB4_2
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; CHECK-NEXT: # %bb.1: # %t
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_2: # %f
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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%tst = icmp ne i32 %a, 5
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br i1 %tst, label %t, label %f
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define i32 @select_beqc(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: select_beqc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.beqc a0, 5, .LBB5_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a1, a2
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: ret
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%tst = icmp eq i32 %a, 5
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%ret = select i1 %tst, i32 %b, i32 %c
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ret i32 %ret
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}
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; NDS.BNEC
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define i32 @bnec(i32 %a) nounwind {
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; CHECK-LABEL: bnec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bnec a0, 5, .LBB6_2
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; CHECK-NEXT: # %bb.1: # %t
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB6_2: # %f
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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%tst = icmp eq i32 %a, 5
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br i1 %tst, label %t, label %f
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f:
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ret i32 0
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t:
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ret i32 1
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}
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define i32 @select_bnec(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: select_bnec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bnec a0, 5, .LBB7_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a1, a2
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; CHECK-NEXT: .LBB7_2:
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: ret
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%tst = icmp ne i32 %a, 5
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%ret = select i1 %tst, i32 %b, i32 %c
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ret i32 %ret
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}
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; NDS.BFOZ
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; MSB >= LSB
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define i32 @bfoz_from_and_i32(i32 %x) {
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; CHECK-LABEL: bfoz_from_and_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 11, 0
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; CHECK-NEXT: ret
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%a = and i32 %x, 4095
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ret i32 %a
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}
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define i64 @bfoz_from_and_i64(i64 %x) {
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; CHECK-LABEL: bfoz_from_and_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 11, 0
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; CHECK-NEXT: li a1, 0
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; CHECK-NEXT: ret
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%a = and i64 %x, 4095
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ret i64 %a
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}
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define i32 @bfoz_from_and_lshr_i32(i32 %x) {
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; CHECK-LABEL: bfoz_from_and_lshr_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 25, 23
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; CHECK-NEXT: ret
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%shifted = lshr i32 %x, 23
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%masked = and i32 %shifted, 7
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ret i32 %masked
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}
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define i64 @bfoz_from_and_lshr_i64(i64 %x) {
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; CHECK-LABEL: bfoz_from_and_lshr_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a1, 25, 14
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; CHECK-NEXT: li a1, 0
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; CHECK-NEXT: ret
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%shifted = lshr i64 %x, 46
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%masked = and i64 %shifted, 4095
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ret i64 %masked
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}
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define i32 @bfoz_from_lshr_and_i32(i32 %x) {
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; CHECK-LABEL: bfoz_from_lshr_and_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 23, 12
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; CHECK-NEXT: ret
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%masked = and i32 %x, 16773120
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%shifted = lshr i32 %masked, 12
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ret i32 %shifted
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}
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define i64 @bfoz_from_lshr_and_i64(i64 %x) {
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; CHECK-LABEL: bfoz_from_lshr_and_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a1, a1, 15
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; CHECK-NEXT: srli a0, a0, 24
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; CHECK-NEXT: slli a1, a1, 8
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; CHECK-NEXT: or a0, a0, a1
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; CHECK-NEXT: li a1, 0
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; CHECK-NEXT: ret
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%masked = and i64 %x, 68702699520
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%shifted = lshr i64 %masked, 24
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ret i64 %shifted
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}
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; MSB = 0
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define i32 @bfoz_from_and_shl_with_msb_zero_i32(i32 %x) {
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; CHECK-LABEL: bfoz_from_and_shl_with_msb_zero_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 0, 15
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; CHECK-NEXT: ret
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%shifted = shl i32 %x, 15
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%masked = and i32 %shifted, 32768
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ret i32 %masked
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}
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define i32 @bfoz_from_lshr_shl_with_msb_zero_i32(i32 %x) {
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; CHECK-LABEL: bfoz_from_lshr_shl_with_msb_zero_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 0, 18
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; CHECK-NEXT: ret
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%shl = shl i32 %x, 31
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%lshr = lshr i32 %shl, 13
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ret i32 %lshr
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}
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; MSB < LSB
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define i32 @bfoz_from_and_shl_i32(i32 %x) {
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; CHECK-LABEL: bfoz_from_and_shl_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 12, 23
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; CHECK-NEXT: ret
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%shifted = shl i32 %x, 12
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%masked = and i32 %shifted, 16773120
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ret i32 %masked
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}
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define i32 @bfoz_from_lshr_shl_i32(i32 %x) {
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; CHECK-LABEL: bfoz_from_lshr_shl_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfoz a0, a0, 19, 24
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; CHECK-NEXT: ret
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%shl = shl i32 %x, 26
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%lshr = lshr i32 %shl, 7
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ret i32 %lshr
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}
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; NDS.BFOS
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; MSB >= LSB
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define i32 @bfos_from_ashr_shl_i32(i32 %x) {
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; CHECK-LABEL: bfos_from_ashr_shl_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 23, 16
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; CHECK-NEXT: ret
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%shl = shl i32 %x, 8
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%ashr = ashr i32 %shl, 24
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ret i32 %ashr
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}
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define i32 @bfos_from_ashr_sexti8_i32(i8 %x) {
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; CHECK-LABEL: bfos_from_ashr_sexti8_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 7, 5
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; CHECK-NEXT: ret
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%sext = sext i8 %x to i32
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%ashr = ashr i32 %sext, 5
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ret i32 %ashr
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}
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define i32 @bfos_from_ashr_sexti16_i32(i16 %x) {
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; CHECK-LABEL: bfos_from_ashr_sexti16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 15, 11
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; CHECK-NEXT: ret
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%sext = sext i16 %x to i32
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%ashr = ashr i32 %sext, 11
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ret i32 %ashr
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}
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; MSB = 0
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define i32 @bfos_from_ashr_shl_with_msb_zero_insert_i32(i32 %x) {
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; CHECK-LABEL: bfos_from_ashr_shl_with_msb_zero_insert_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 0, 14
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; CHECK-NEXT: ret
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%shl = shl i32 %x, 31
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%lshr = ashr i32 %shl, 17
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ret i32 %lshr
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}
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; MSB < LSB
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define i32 @bfos_from_ashr_shl_insert_i32(i32 %x) {
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; CHECK-LABEL: bfos_from_ashr_shl_insert_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 18, 20
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; CHECK-NEXT: ret
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%shl = shl i32 %x, 29
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%lshr = ashr i32 %shl, 11
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ret i32 %lshr
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}
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; sext
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define i32 @sexti1_i32(i32 %a) {
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; CHECK-LABEL: sexti1_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 0, 0
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; CHECK-NEXT: ret
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%shl = shl i32 %a, 31
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%shr = ashr exact i32 %shl, 31
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ret i32 %shr
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}
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define i32 @sexti1_i32_2(i1 %a) {
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; CHECK-LABEL: sexti1_i32_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 0, 0
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; CHECK-NEXT: ret
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%1 = sext i1 %a to i32
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ret i32 %1
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}
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; Make sure we don't use not+nds.bfos
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define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
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; CHECK-LABEL: sexti1_i32_setcc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srli a0, a0, 31
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: zext.b a0, a0
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; CHECK-NEXT: ret
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%icmp = icmp sgt i32 %a, -1
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%sext = sext i1 %icmp to i8
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ret i8 %sext
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}
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; Make sure we don't use seqz+nds.bfos instead of snez+addi
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define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
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; CHECK-LABEL: sexti1_i32_setcc_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xor a0, a0, a1
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: ret
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%icmp = icmp eq i32 %a, %b
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%sext = sext i1 %icmp to i32
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ret i32 %sext
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}
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; Make sure we don't use nds.bfos instead of neg.
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define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
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; CHECK-LABEL: sexti1_i32_setcc_3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slt a0, a0, a1
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; CHECK-NEXT: neg a0, a0
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; CHECK-NEXT: ret
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%icmp = icmp slt i32 %a, %b
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%sext = sext i1 %icmp to i32
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ret i32 %sext
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}
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define i32 @sexti8_i32(i32 %a) {
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; CHECK-LABEL: sexti8_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 7, 0
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; CHECK-NEXT: ret
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%shl = shl i32 %a, 24
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%shr = ashr exact i32 %shl, 24
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ret i32 %shr
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}
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define i32 @sexti8_i32_2(i8 %a) {
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; CHECK-LABEL: sexti8_i32_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 7, 0
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; CHECK-NEXT: ret
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%1 = sext i8 %a to i32
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ret i32 %1
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}
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define i32 @sexti16_i32(i32 %a) {
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; CHECK-LABEL: sexti16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 15, 0
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; CHECK-NEXT: ret
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%shl = shl i32 %a, 16
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%shr = ashr exact i32 %shl, 16
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ret i32 %shr
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}
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define i32 @sexti16_i32_2(i16 %a) {
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; CHECK-LABEL: sexti16_i32_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 15, 0
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; CHECK-NEXT: ret
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%1 = sext i16 %a to i32
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ret i32 %1
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}
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define i64 @sexti1_i64(i64 %a) {
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; CHECK-LABEL: sexti1_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 0, 0
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: ret
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%shl = shl i64 %a, 63
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%shr = ashr exact i64 %shl, 63
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ret i64 %shr
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}
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define i64 @sexti1_i64_2(i1 %a) {
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; CHECK-LABEL: sexti1_i64_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 0, 0
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: ret
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%1 = sext i1 %a to i64
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ret i64 %1
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}
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define i64 @sexti8_i64(i64 %a) {
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; CHECK-LABEL: sexti8_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 7, 0
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; CHECK-NEXT: srai a1, a0, 31
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; CHECK-NEXT: ret
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%shl = shl i64 %a, 56
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%shr = ashr exact i64 %shl, 56
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ret i64 %shr
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}
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define i64 @sexti8_i64_2(i8 %a) {
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; CHECK-LABEL: sexti8_i64_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nds.bfos a0, a0, 7, 0
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; CHECK-NEXT: srai a1, a0, 31
|
|
; CHECK-NEXT: ret
|
|
%1 = sext i8 %a to i64
|
|
ret i64 %1
|
|
}
|
|
|
|
define i64 @sexti16_i64(i64 %a) {
|
|
; CHECK-LABEL: sexti16_i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
|
|
; CHECK-NEXT: srai a1, a0, 31
|
|
; CHECK-NEXT: ret
|
|
%shl = shl i64 %a, 48
|
|
%shr = ashr exact i64 %shl, 48
|
|
ret i64 %shr
|
|
}
|
|
|
|
define i64 @sexti16_i64_2(i16 %a) {
|
|
; CHECK-LABEL: sexti16_i64_2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
|
|
; CHECK-NEXT: srai a1, a0, 31
|
|
; CHECK-NEXT: ret
|
|
%1 = sext i16 %a to i64
|
|
ret i64 %1
|
|
}
|
|
|
|
define i64 @sexti32_i64(i64 %a) {
|
|
; CHECK-LABEL: sexti32_i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: srai a1, a0, 31
|
|
; CHECK-NEXT: ret
|
|
%shl = shl i64 %a, 32
|
|
%shr = ashr exact i64 %shl, 32
|
|
ret i64 %shr
|
|
}
|
|
|
|
define i64 @sexti32_i64_2(i32 %a) {
|
|
; CHECK-LABEL: sexti32_i64_2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: srai a1, a0, 31
|
|
; CHECK-NEXT: ret
|
|
%1 = sext i32 %a to i64
|
|
ret i64 %1
|
|
}
|