655 lines
19 KiB
LLVM
655 lines
19 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBB,RV32XTHEADBB-NOB
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb,+b -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XTHEADBB,RV32XTHEADBB-B
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declare i32 @llvm.ctlz.i32(i32, i1)
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define i32 @ctlz_i32(i32 %a) nounwind {
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; RV32I-LABEL: ctlz_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a0, .LBB0_2
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; RV32I-NEXT: # %bb.1: # %cond.false
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; RV32I-NEXT: srli a1, a0, 1
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; RV32I-NEXT: lui a2, 349525
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: addi a1, a2, 1365
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; RV32I-NEXT: srli a2, a0, 2
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: srli a2, a0, 4
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: srli a2, a0, 8
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: srli a2, a0, 16
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: srli a2, a0, 1
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; RV32I-NEXT: and a1, a2, a1
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; RV32I-NEXT: lui a2, 209715
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; RV32I-NEXT: addi a2, a2, 819
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: and a1, a0, a2
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; RV32I-NEXT: srli a0, a0, 2
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: lui a2, 61681
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: srli a1, a0, 4
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: addi a1, a2, -241
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 8
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 16
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srli a0, a0, 24
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: li a0, 32
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; RV32I-NEXT: ret
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;
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; RV32XTHEADBB-NOB-LABEL: ctlz_i32:
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; RV32XTHEADBB-NOB: # %bb.0:
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; RV32XTHEADBB-NOB-NEXT: th.ff1 a0, a0
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; RV32XTHEADBB-NOB-NEXT: ret
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;
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; RV32XTHEADBB-B-LABEL: ctlz_i32:
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; RV32XTHEADBB-B: # %bb.0:
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; RV32XTHEADBB-B-NEXT: clz a0, a0
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; RV32XTHEADBB-B-NEXT: ret
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%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
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ret i32 %1
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}
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declare i64 @llvm.ctlz.i64(i64, i1)
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define i64 @ctlz_i64(i64 %a) nounwind {
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; RV32I-LABEL: ctlz_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: or a2, a0, a1
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; RV32I-NEXT: beqz a2, .LBB1_3
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; RV32I-NEXT: # %bb.1: # %cond.false
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; RV32I-NEXT: lui a2, 349525
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; RV32I-NEXT: lui a3, 209715
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; RV32I-NEXT: lui a5, 61681
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; RV32I-NEXT: addi a4, a2, 1365
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; RV32I-NEXT: addi a3, a3, 819
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; RV32I-NEXT: addi a2, a5, -241
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; RV32I-NEXT: bnez a1, .LBB1_4
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; RV32I-NEXT: # %bb.2: # %cond.false
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; RV32I-NEXT: srli a1, a0, 1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 2
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 4
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 8
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 16
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: srli a1, a0, 1
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; RV32I-NEXT: and a1, a1, a4
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: and a1, a0, a3
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; RV32I-NEXT: srli a0, a0, 2
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; RV32I-NEXT: and a0, a0, a3
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: srli a1, a0, 4
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: slli a1, a0, 8
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 16
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srli a0, a0, 24
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; RV32I-NEXT: addi a0, a0, 32
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB1_3:
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: li a0, 64
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB1_4:
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; RV32I-NEXT: srli a0, a1, 1
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: srli a1, a0, 2
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 4
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 8
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: srli a1, a0, 16
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: srli a1, a0, 1
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; RV32I-NEXT: and a1, a1, a4
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: and a1, a0, a3
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; RV32I-NEXT: srli a0, a0, 2
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; RV32I-NEXT: and a0, a0, a3
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: srli a1, a0, 4
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: slli a1, a0, 8
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 16
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: srli a0, a0, 24
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV32XTHEADBB-NOB-LABEL: ctlz_i64:
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; RV32XTHEADBB-NOB: # %bb.0:
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; RV32XTHEADBB-NOB-NEXT: bnez a1, .LBB1_2
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; RV32XTHEADBB-NOB-NEXT: # %bb.1:
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; RV32XTHEADBB-NOB-NEXT: th.ff1 a0, a0
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; RV32XTHEADBB-NOB-NEXT: addi a0, a0, 32
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; RV32XTHEADBB-NOB-NEXT: li a1, 0
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; RV32XTHEADBB-NOB-NEXT: ret
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; RV32XTHEADBB-NOB-NEXT: .LBB1_2:
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; RV32XTHEADBB-NOB-NEXT: th.ff1 a0, a1
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; RV32XTHEADBB-NOB-NEXT: li a1, 0
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; RV32XTHEADBB-NOB-NEXT: ret
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;
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; RV32XTHEADBB-B-LABEL: ctlz_i64:
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; RV32XTHEADBB-B: # %bb.0:
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; RV32XTHEADBB-B-NEXT: bnez a1, .LBB1_2
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; RV32XTHEADBB-B-NEXT: # %bb.1:
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; RV32XTHEADBB-B-NEXT: clz a0, a0
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; RV32XTHEADBB-B-NEXT: addi a0, a0, 32
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; RV32XTHEADBB-B-NEXT: li a1, 0
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; RV32XTHEADBB-B-NEXT: ret
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; RV32XTHEADBB-B-NEXT: .LBB1_2:
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; RV32XTHEADBB-B-NEXT: clz a0, a1
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; RV32XTHEADBB-B-NEXT: li a1, 0
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; RV32XTHEADBB-B-NEXT: ret
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%1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
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ret i64 %1
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}
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declare i32 @llvm.cttz.i32(i32, i1)
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define i32 @cttz_i32(i32 %a) nounwind {
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; RV32I-LABEL: cttz_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a0, .LBB2_2
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; RV32I-NEXT: # %bb.1: # %cond.false
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: neg a1, a0
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: lui a1, 30667
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; RV32I-NEXT: addi a1, a1, 1329
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; RV32I-NEXT: call __mulsi3
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; RV32I-NEXT: srli a0, a0, 27
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; RV32I-NEXT: lui a1, %hi(.LCPI2_0)
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; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0)
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: lbu a0, 0(a0)
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; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: li a0, 32
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; RV32I-NEXT: ret
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;
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; RV32XTHEADBB-NOB-LABEL: cttz_i32:
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; RV32XTHEADBB-NOB: # %bb.0:
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; RV32XTHEADBB-NOB-NEXT: beqz a0, .LBB2_2
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; RV32XTHEADBB-NOB-NEXT: # %bb.1: # %cond.false
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; RV32XTHEADBB-NOB-NEXT: addi a1, a0, -1
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; RV32XTHEADBB-NOB-NEXT: not a0, a0
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; RV32XTHEADBB-NOB-NEXT: and a0, a0, a1
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; RV32XTHEADBB-NOB-NEXT: th.ff1 a0, a0
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; RV32XTHEADBB-NOB-NEXT: li a1, 32
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; RV32XTHEADBB-NOB-NEXT: sub a0, a1, a0
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; RV32XTHEADBB-NOB-NEXT: ret
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; RV32XTHEADBB-NOB-NEXT: .LBB2_2:
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; RV32XTHEADBB-NOB-NEXT: li a0, 32
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; RV32XTHEADBB-NOB-NEXT: ret
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;
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; RV32XTHEADBB-B-LABEL: cttz_i32:
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; RV32XTHEADBB-B: # %bb.0:
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; RV32XTHEADBB-B-NEXT: ctz a0, a0
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; RV32XTHEADBB-B-NEXT: ret
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%1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)
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ret i32 %1
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}
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declare i64 @llvm.cttz.i64(i64, i1)
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define i64 @cttz_i64(i64 %a) nounwind {
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; RV32I-LABEL: cttz_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -32
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; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
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; RV32I-NEXT: mv s0, a1
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; RV32I-NEXT: or a1, a0, a1
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; RV32I-NEXT: beqz a1, .LBB3_3
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; RV32I-NEXT: # %bb.1: # %cond.false
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; RV32I-NEXT: neg a1, a0
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; RV32I-NEXT: and a1, a0, a1
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; RV32I-NEXT: lui a2, 30667
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; RV32I-NEXT: addi s2, a2, 1329
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; RV32I-NEXT: mv s4, a0
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: mv a1, s2
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; RV32I-NEXT: call __mulsi3
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; RV32I-NEXT: mv s1, a0
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; RV32I-NEXT: lui s3, %hi(.LCPI3_0)
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; RV32I-NEXT: addi s3, s3, %lo(.LCPI3_0)
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; RV32I-NEXT: neg a0, s0
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; RV32I-NEXT: and a0, s0, a0
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; RV32I-NEXT: mv a1, s2
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; RV32I-NEXT: call __mulsi3
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; RV32I-NEXT: bnez s4, .LBB3_4
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; RV32I-NEXT: # %bb.2: # %cond.false
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; RV32I-NEXT: srli a0, a0, 27
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; RV32I-NEXT: add a0, s3, a0
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; RV32I-NEXT: lbu a0, 0(a0)
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; RV32I-NEXT: addi a0, a0, 32
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; RV32I-NEXT: j .LBB3_5
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; RV32I-NEXT: .LBB3_3:
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; RV32I-NEXT: li a0, 64
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; RV32I-NEXT: j .LBB3_6
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; RV32I-NEXT: .LBB3_4:
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; RV32I-NEXT: srli s1, s1, 27
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; RV32I-NEXT: add s1, s3, s1
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; RV32I-NEXT: lbu a0, 0(s1)
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; RV32I-NEXT: .LBB3_5: # %cond.false
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: .LBB3_6: # %cond.end
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; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 32
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; RV32I-NEXT: ret
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;
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; RV32XTHEADBB-NOB-LABEL: cttz_i64:
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; RV32XTHEADBB-NOB: # %bb.0:
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; RV32XTHEADBB-NOB-NEXT: or a2, a0, a1
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; RV32XTHEADBB-NOB-NEXT: beqz a2, .LBB3_3
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; RV32XTHEADBB-NOB-NEXT: # %bb.1: # %cond.false
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; RV32XTHEADBB-NOB-NEXT: bnez a0, .LBB3_4
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; RV32XTHEADBB-NOB-NEXT: # %bb.2: # %cond.false
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; RV32XTHEADBB-NOB-NEXT: addi a0, a1, -1
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; RV32XTHEADBB-NOB-NEXT: not a1, a1
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; RV32XTHEADBB-NOB-NEXT: and a0, a1, a0
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; RV32XTHEADBB-NOB-NEXT: th.ff1 a0, a0
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; RV32XTHEADBB-NOB-NEXT: li a1, 64
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; RV32XTHEADBB-NOB-NEXT: j .LBB3_5
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; RV32XTHEADBB-NOB-NEXT: .LBB3_3:
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; RV32XTHEADBB-NOB-NEXT: li a1, 0
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; RV32XTHEADBB-NOB-NEXT: li a0, 64
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; RV32XTHEADBB-NOB-NEXT: ret
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; RV32XTHEADBB-NOB-NEXT: .LBB3_4:
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; RV32XTHEADBB-NOB-NEXT: addi a1, a0, -1
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; RV32XTHEADBB-NOB-NEXT: not a0, a0
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; RV32XTHEADBB-NOB-NEXT: and a0, a0, a1
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; RV32XTHEADBB-NOB-NEXT: th.ff1 a0, a0
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; RV32XTHEADBB-NOB-NEXT: li a1, 32
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; RV32XTHEADBB-NOB-NEXT: .LBB3_5: # %cond.false
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; RV32XTHEADBB-NOB-NEXT: sub a0, a1, a0
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; RV32XTHEADBB-NOB-NEXT: li a1, 0
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; RV32XTHEADBB-NOB-NEXT: ret
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;
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; RV32XTHEADBB-B-LABEL: cttz_i64:
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; RV32XTHEADBB-B: # %bb.0:
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; RV32XTHEADBB-B-NEXT: bnez a0, .LBB3_2
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; RV32XTHEADBB-B-NEXT: # %bb.1:
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; RV32XTHEADBB-B-NEXT: ctz a0, a1
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; RV32XTHEADBB-B-NEXT: addi a0, a0, 32
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; RV32XTHEADBB-B-NEXT: li a1, 0
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; RV32XTHEADBB-B-NEXT: ret
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; RV32XTHEADBB-B-NEXT: .LBB3_2:
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; RV32XTHEADBB-B-NEXT: ctz a0, a0
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; RV32XTHEADBB-B-NEXT: li a1, 0
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; RV32XTHEADBB-B-NEXT: ret
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%1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
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ret i64 %1
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}
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define i32 @sexti1_i32(i32 %a) nounwind {
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; RV32I-LABEL: sexti1_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 31
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; RV32I-NEXT: srai a0, a0, 31
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; RV32I-NEXT: ret
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;
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; RV32XTHEADBB-LABEL: sexti1_i32:
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; RV32XTHEADBB: # %bb.0:
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; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0
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; RV32XTHEADBB-NEXT: ret
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%shl = shl i32 %a, 31
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%shr = ashr exact i32 %shl, 31
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ret i32 %shr
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}
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define i32 @sexti1_i32_2(i1 %a) nounwind {
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; RV32I-LABEL: sexti1_i32_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 31
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; RV32I-NEXT: srai a0, a0, 31
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-LABEL: sexti1_i32_2:
|
|
; RV32XTHEADBB: # %bb.0:
|
|
; RV32XTHEADBB-NEXT: th.ext a0, a0, 0, 0
|
|
; RV32XTHEADBB-NEXT: ret
|
|
%sext = sext i1 %a to i32
|
|
ret i32 %sext
|
|
}
|
|
|
|
; Make sure we don't use not+th.ext
|
|
define zeroext i8 @sexti1_i32_setcc(i32 signext %a) {
|
|
; CHECK-LABEL: sexti1_i32_setcc:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: srli a0, a0, 31
|
|
; CHECK-NEXT: addi a0, a0, -1
|
|
; CHECK-NEXT: zext.b a0, a0
|
|
; CHECK-NEXT: ret
|
|
%icmp = icmp sgt i32 %a, -1
|
|
%sext = sext i1 %icmp to i8
|
|
ret i8 %sext
|
|
}
|
|
|
|
; Make sure we don't use seqz+th.ext instead of snez+addi
|
|
define i32 @sexti1_i32_setcc_2(i32 %a, i32 %b) {
|
|
; CHECK-LABEL: sexti1_i32_setcc_2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: xor a0, a0, a1
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: addi a0, a0, -1
|
|
; CHECK-NEXT: ret
|
|
%icmp = icmp eq i32 %a, %b
|
|
%sext = sext i1 %icmp to i32
|
|
ret i32 %sext
|
|
}
|
|
|
|
; Make sure we don't use th.ext instead of neg.
|
|
define i32 @sexti1_i32_setcc_3(i32 %a, i32 %b) {
|
|
; CHECK-LABEL: sexti1_i32_setcc_3:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: slt a0, a0, a1
|
|
; CHECK-NEXT: neg a0, a0
|
|
; CHECK-NEXT: ret
|
|
%icmp = icmp slt i32 %a, %b
|
|
%sext = sext i1 %icmp to i32
|
|
ret i32 %sext
|
|
}
|
|
|
|
define i32 @sextb_i32(i32 %a) nounwind {
|
|
; RV32I-LABEL: sextb_i32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a0, a0, 24
|
|
; RV32I-NEXT: srai a0, a0, 24
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: sextb_i32:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.ext a0, a0, 7, 0
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: sextb_i32:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: sext.b a0, a0
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%shl = shl i32 %a, 24
|
|
%shr = ashr exact i32 %shl, 24
|
|
ret i32 %shr
|
|
}
|
|
|
|
define i64 @sextb_i64(i64 %a) nounwind {
|
|
; RV32I-LABEL: sextb_i64:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a1, a0, 24
|
|
; RV32I-NEXT: srai a0, a1, 24
|
|
; RV32I-NEXT: srai a1, a1, 31
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: sextb_i64:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.ext a0, a0, 7, 0
|
|
; RV32XTHEADBB-NOB-NEXT: srai a1, a0, 31
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: sextb_i64:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: sext.b a0, a0
|
|
; RV32XTHEADBB-B-NEXT: srai a1, a0, 31
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%shl = shl i64 %a, 56
|
|
%shr = ashr exact i64 %shl, 56
|
|
ret i64 %shr
|
|
}
|
|
|
|
define i32 @sexth_i32(i32 %a) nounwind {
|
|
; RV32I-LABEL: sexth_i32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a0, a0, 16
|
|
; RV32I-NEXT: srai a0, a0, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: sexth_i32:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.ext a0, a0, 15, 0
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: sexth_i32:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: sext.h a0, a0
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%shl = shl i32 %a, 16
|
|
%shr = ashr exact i32 %shl, 16
|
|
ret i32 %shr
|
|
}
|
|
|
|
define i32 @no_sexth_i32(i32 %a) nounwind {
|
|
; CHECK-LABEL: no_sexth_i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: slli a0, a0, 17
|
|
; CHECK-NEXT: srai a0, a0, 16
|
|
; CHECK-NEXT: ret
|
|
%shl = shl i32 %a, 17
|
|
%shr = ashr exact i32 %shl, 16
|
|
ret i32 %shr
|
|
}
|
|
|
|
define i64 @sexth_i64(i64 %a) nounwind {
|
|
; RV32I-LABEL: sexth_i64:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a1, a0, 16
|
|
; RV32I-NEXT: srai a0, a1, 16
|
|
; RV32I-NEXT: srai a1, a1, 31
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: sexth_i64:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.ext a0, a0, 15, 0
|
|
; RV32XTHEADBB-NOB-NEXT: srai a1, a0, 31
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: sexth_i64:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: sext.h a0, a0
|
|
; RV32XTHEADBB-B-NEXT: srai a1, a0, 31
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%shl = shl i64 %a, 48
|
|
%shr = ashr exact i64 %shl, 48
|
|
ret i64 %shr
|
|
}
|
|
|
|
define i64 @no_sexth_i64(i64 %a) nounwind {
|
|
; CHECK-LABEL: no_sexth_i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: slli a1, a0, 17
|
|
; CHECK-NEXT: srai a0, a1, 16
|
|
; CHECK-NEXT: srai a1, a1, 31
|
|
; CHECK-NEXT: ret
|
|
%shl = shl i64 %a, 49
|
|
%shr = ashr exact i64 %shl, 48
|
|
ret i64 %shr
|
|
}
|
|
|
|
define i32 @sext_sextinreg_sra(i16 %a) nounwind {
|
|
; RV32I-LABEL: sext_sextinreg_sra:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a0, a0, 16
|
|
; RV32I-NEXT: srai a0, a0, 26
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-LABEL: sext_sextinreg_sra:
|
|
; RV32XTHEADBB: # %bb.0:
|
|
; RV32XTHEADBB-NEXT: th.ext a0, a0, 15, 10
|
|
; RV32XTHEADBB-NEXT: ret
|
|
%sext = sext i16 %a to i32
|
|
%shr = ashr exact i32 %sext, 10
|
|
ret i32 %shr
|
|
}
|
|
|
|
define i32 @sext_sextinreg_sra_2(i16 %a) nounwind {
|
|
; RV32I-LABEL: sext_sextinreg_sra_2:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a0, a0, 16
|
|
; RV32I-NEXT: srai a0, a0, 31
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-LABEL: sext_sextinreg_sra_2:
|
|
; RV32XTHEADBB: # %bb.0:
|
|
; RV32XTHEADBB-NEXT: th.ext a0, a0, 15, 15
|
|
; RV32XTHEADBB-NEXT: ret
|
|
%sext = sext i16 %a to i32
|
|
%shr = ashr exact i32 %sext, 24
|
|
ret i32 %shr
|
|
}
|
|
|
|
define i32 @zexth_i32(i32 %a) nounwind {
|
|
; RV32I-LABEL: zexth_i32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a0, a0, 16
|
|
; RV32I-NEXT: srli a0, a0, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: zexth_i32:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.extu a0, a0, 15, 0
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: zexth_i32:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: zext.h a0, a0
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%and = and i32 %a, 65535
|
|
ret i32 %and
|
|
}
|
|
|
|
define i64 @zexth_i64(i64 %a) nounwind {
|
|
; RV32I-LABEL: zexth_i64:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a0, a0, 16
|
|
; RV32I-NEXT: srli a0, a0, 16
|
|
; RV32I-NEXT: li a1, 0
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: zexth_i64:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.extu a0, a0, 15, 0
|
|
; RV32XTHEADBB-NOB-NEXT: li a1, 0
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: zexth_i64:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: zext.h a0, a0
|
|
; RV32XTHEADBB-B-NEXT: li a1, 0
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%and = and i64 %a, 65535
|
|
ret i64 %and
|
|
}
|
|
|
|
declare i32 @llvm.bswap.i32(i32)
|
|
|
|
define i32 @bswap_i32(i32 %a) nounwind {
|
|
; RV32I-LABEL: bswap_i32:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: srli a1, a0, 8
|
|
; RV32I-NEXT: lui a2, 16
|
|
; RV32I-NEXT: srli a3, a0, 24
|
|
; RV32I-NEXT: addi a2, a2, -256
|
|
; RV32I-NEXT: and a1, a1, a2
|
|
; RV32I-NEXT: and a2, a0, a2
|
|
; RV32I-NEXT: or a1, a1, a3
|
|
; RV32I-NEXT: slli a2, a2, 8
|
|
; RV32I-NEXT: slli a0, a0, 24
|
|
; RV32I-NEXT: or a0, a0, a2
|
|
; RV32I-NEXT: or a0, a0, a1
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: bswap_i32:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.rev a0, a0
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: bswap_i32:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: rev8 a0, a0
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%1 = tail call i32 @llvm.bswap.i32(i32 %a)
|
|
ret i32 %1
|
|
}
|
|
|
|
declare i64 @llvm.bswap.i64(i64)
|
|
|
|
define i64 @bswap_i64(i64 %a) {
|
|
; RV32I-LABEL: bswap_i64:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: srli a2, a1, 8
|
|
; RV32I-NEXT: lui a3, 16
|
|
; RV32I-NEXT: srli a4, a1, 24
|
|
; RV32I-NEXT: srli a5, a0, 8
|
|
; RV32I-NEXT: addi a3, a3, -256
|
|
; RV32I-NEXT: and a2, a2, a3
|
|
; RV32I-NEXT: or a2, a2, a4
|
|
; RV32I-NEXT: srli a4, a0, 24
|
|
; RV32I-NEXT: and a5, a5, a3
|
|
; RV32I-NEXT: or a4, a5, a4
|
|
; RV32I-NEXT: slli a5, a1, 24
|
|
; RV32I-NEXT: and a1, a1, a3
|
|
; RV32I-NEXT: slli a1, a1, 8
|
|
; RV32I-NEXT: or a1, a5, a1
|
|
; RV32I-NEXT: and a3, a0, a3
|
|
; RV32I-NEXT: slli a0, a0, 24
|
|
; RV32I-NEXT: slli a3, a3, 8
|
|
; RV32I-NEXT: or a3, a0, a3
|
|
; RV32I-NEXT: or a0, a1, a2
|
|
; RV32I-NEXT: or a1, a3, a4
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-NOB-LABEL: bswap_i64:
|
|
; RV32XTHEADBB-NOB: # %bb.0:
|
|
; RV32XTHEADBB-NOB-NEXT: th.rev a2, a1
|
|
; RV32XTHEADBB-NOB-NEXT: th.rev a1, a0
|
|
; RV32XTHEADBB-NOB-NEXT: mv a0, a2
|
|
; RV32XTHEADBB-NOB-NEXT: ret
|
|
;
|
|
; RV32XTHEADBB-B-LABEL: bswap_i64:
|
|
; RV32XTHEADBB-B: # %bb.0:
|
|
; RV32XTHEADBB-B-NEXT: rev8 a2, a1
|
|
; RV32XTHEADBB-B-NEXT: rev8 a1, a0
|
|
; RV32XTHEADBB-B-NEXT: mv a0, a2
|
|
; RV32XTHEADBB-B-NEXT: ret
|
|
%1 = call i64 @llvm.bswap.i64(i64 %a)
|
|
ret i64 %1
|
|
}
|