364028a1a5
Remove them from experimental. See also: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc Reviewers: kito-cheng Reviewed By: kito-cheng Pull Request: https://github.com/llvm/llvm-project/pull/87966
89 lines
2.5 KiB
LLVM
89 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+zimop -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZIMOP
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declare i64 @llvm.riscv.mopr.i64(i64 %a, i64 %b)
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define i64 @mopr0_64(i64 %a) nounwind {
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; RV64ZIMOP-LABEL: mopr0_64:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.r.0 a0, a0
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; RV64ZIMOP-NEXT: ret
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%tmp = call i64 @llvm.riscv.mopr.i64(i64 %a, i64 0)
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ret i64 %tmp
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}
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define i64 @mopr31_64(i64 %a) nounwind {
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; RV64ZIMOP-LABEL: mopr31_64:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.r.31 a0, a0
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; RV64ZIMOP-NEXT: ret
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%tmp = call i64 @llvm.riscv.mopr.i64(i64 %a, i64 31)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.moprr.i64(i64 %a, i64 %b, i64 %c)
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define i64 @moprr0_64(i64 %a, i64 %b) nounwind {
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; RV64ZIMOP-LABEL: moprr0_64:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.rr.0 a0, a0, a1
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; RV64ZIMOP-NEXT: ret
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%tmp = call i64 @llvm.riscv.moprr.i64(i64 %a, i64 %b, i64 0)
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ret i64 %tmp
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}
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define i64 @moprr7_64(i64 %a, i64 %b) nounwind {
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; RV64ZIMOP-LABEL: moprr7_64:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.rr.7 a0, a0, a1
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; RV64ZIMOP-NEXT: ret
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%tmp = call i64 @llvm.riscv.moprr.i64(i64 %a, i64 %b, i64 7)
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ret i64 %tmp
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}
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declare i32 @llvm.riscv.mopr.i32(i32 %a, i32 %b)
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define signext i32 @mopr0_32(i32 signext %a) nounwind {
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; RV64ZIMOP-LABEL: mopr0_32:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.r.0 a0, a0
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; RV64ZIMOP-NEXT: sext.w a0, a0
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; RV64ZIMOP-NEXT: ret
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%tmp = call i32 @llvm.riscv.mopr.i32(i32 %a, i32 0)
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ret i32 %tmp
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}
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define signext i32 @mopr31_32(i32 signext %a) nounwind {
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; RV64ZIMOP-LABEL: mopr31_32:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.r.31 a0, a0
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; RV64ZIMOP-NEXT: sext.w a0, a0
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; RV64ZIMOP-NEXT: ret
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%tmp = call i32 @llvm.riscv.mopr.i32(i32 %a, i32 31)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.moprr.i32(i32 %a, i32 %b, i32 %c)
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define signext i32 @moprr0_32(i32 signext %a, i32 signext %b) nounwind {
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; RV64ZIMOP-LABEL: moprr0_32:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.rr.0 a0, a0, a1
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; RV64ZIMOP-NEXT: sext.w a0, a0
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; RV64ZIMOP-NEXT: ret
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%tmp = call i32 @llvm.riscv.moprr.i32(i32 %a, i32 %b, i32 0)
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ret i32 %tmp
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}
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define signext i32 @moprr7_32(i32 signext %a, i32 signext %b) nounwind {
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; RV64ZIMOP-LABEL: moprr7_32:
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; RV64ZIMOP: # %bb.0:
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; RV64ZIMOP-NEXT: mop.rr.7 a0, a0, a1
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; RV64ZIMOP-NEXT: sext.w a0, a0
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; RV64ZIMOP-NEXT: ret
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%tmp = call i32 @llvm.riscv.moprr.i32(i32 %a, i32 %b, i32 7)
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ret i32 %tmp
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}
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