18782db4c9
(seteq (and X, 1<<XLEN-1), 0) -> (xori (srli X, XLEN-1), 1)
(seteq (and X, 1<<31), 0) -> (xori (srliw X, 31), 1) // RV64
(setlt X, 0) -> (srli X, XLEN-1) // SRLI is compressible
(setlt (sext X), 0) -> (srliw X, 31) // RV64
316 lines
7.7 KiB
LLVM
316 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 %s -o - | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s --check-prefix=RV64
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define i32 @xori64i32(i64 %a) {
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; RV32-LABEL: xori64i32:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a1, a1, 31
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; RV32-NEXT: lui a0, 524288
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: xor a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: xori64i32:
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; RV64: # %bb.0:
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; RV64-NEXT: srai a0, a0, 63
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; RV64-NEXT: lui a1, 524288
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; RV64-NEXT: addiw a1, a1, -1
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: ret
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%shr4 = ashr i64 %a, 63
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%conv5 = trunc i64 %shr4 to i32
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%xor = xor i32 %conv5, 2147483647
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ret i32 %xor
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}
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define i64 @selecti64i64(i64 %a) {
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; RV32-LABEL: selecti64i64:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a1, a1, 31
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; RV32-NEXT: lui a0, 524288
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: xor a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: selecti64i64:
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; RV64: # %bb.0:
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; RV64-NEXT: srai a0, a0, 63
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; RV64-NEXT: lui a1, 524288
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; RV64-NEXT: addiw a1, a1, -1
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: ret
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%c = icmp sgt i64 %a, -1
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%s = select i1 %c, i64 2147483647, i64 -2147483648
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ret i64 %s
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}
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define i32 @selecti64i32(i64 %a) {
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; RV32-LABEL: selecti64i32:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a1, a1, 31
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; RV32-NEXT: xori a0, a1, 1
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; RV32-NEXT: lui a1, 524288
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; RV32-NEXT: sub a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: selecti64i32:
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; RV64: # %bb.0:
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; RV64-NEXT: srai a0, a0, 63
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; RV64-NEXT: lui a1, 524288
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; RV64-NEXT: addiw a1, a1, -1
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: ret
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%c = icmp sgt i64 %a, -1
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%s = select i1 %c, i32 2147483647, i32 -2147483648
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ret i32 %s
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}
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define i64 @selecti32i64(i32 %a) {
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; RV32-LABEL: selecti32i64:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a1, a0, 31
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; RV32-NEXT: lui a0, 524288
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; RV32-NEXT: addi a0, a0, -1
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; RV32-NEXT: xor a0, a1, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: selecti32i64:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 31
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; RV64-NEXT: lui a1, 524288
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; RV64-NEXT: addiw a1, a1, -1
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i64 2147483647, i64 -2147483648
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ret i64 %s
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}
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define i8 @xori32i8(i32 %a) {
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; RV32-LABEL: xori32i8:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a0, a0, 31
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; RV32-NEXT: xori a0, a0, 84
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; RV32-NEXT: ret
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;
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; RV64-LABEL: xori32i8:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 31
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; RV64-NEXT: xori a0, a0, 84
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; RV64-NEXT: ret
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%shr4 = ashr i32 %a, 31
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%conv5 = trunc i32 %shr4 to i8
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%xor = xor i8 %conv5, 84
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ret i8 %xor
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}
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define i32 @selecti32i32(i32 %a) {
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; RV32-LABEL: selecti32i32:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a0, a0, 31
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; RV32-NEXT: xori a0, a0, 84
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; RV32-NEXT: ret
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;
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; RV64-LABEL: selecti32i32:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 31
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; RV64-NEXT: xori a0, a0, 84
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; RV64-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i32 84, i32 -85
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ret i32 %s
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}
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define i8 @selecti32i8(i32 %a) {
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; RV32-LABEL: selecti32i8:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a0, a0, 31
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; RV32-NEXT: xori a0, a0, 84
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; RV32-NEXT: ret
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;
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; RV64-LABEL: selecti32i8:
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; RV64: # %bb.0:
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; RV64-NEXT: sraiw a0, a0, 31
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; RV64-NEXT: xori a0, a0, 84
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; RV64-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i8 84, i8 -85
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ret i8 %s
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}
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define i32 @selecti8i32(i8 %a) {
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; RV32-LABEL: selecti8i32:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 24
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; RV32-NEXT: srai a0, a0, 31
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; RV32-NEXT: xori a0, a0, 84
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; RV32-NEXT: ret
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;
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; RV64-LABEL: selecti8i32:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a0, a0, 56
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; RV64-NEXT: srai a0, a0, 63
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; RV64-NEXT: xori a0, a0, 84
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; RV64-NEXT: ret
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%c = icmp sgt i8 %a, -1
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%s = select i1 %c, i32 84, i32 -85
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ret i32 %s
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}
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define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
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; RV32-LABEL: icmpasreq:
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; RV32: # %bb.0:
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; RV32-NEXT: bltz a0, .LBB8_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: mv a1, a2
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; RV32-NEXT: .LBB8_2:
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; RV32-NEXT: mv a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: icmpasreq:
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; RV64: # %bb.0:
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; RV64-NEXT: sext.w a3, a0
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; RV64-NEXT: mv a0, a1
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; RV64-NEXT: bltz a3, .LBB8_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: mv a0, a2
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; RV64-NEXT: .LBB8_2:
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; RV64-NEXT: ret
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%sh = ashr i32 %input, 31
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%c = icmp eq i32 %sh, -1
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%s = select i1 %c, i32 %a, i32 %b
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ret i32 %s
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}
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define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
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; RV32-LABEL: icmpasrne:
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; RV32: # %bb.0:
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; RV32-NEXT: bgez a0, .LBB9_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: mv a1, a2
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; RV32-NEXT: .LBB9_2:
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; RV32-NEXT: mv a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: icmpasrne:
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; RV64: # %bb.0:
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; RV64-NEXT: sext.w a3, a0
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; RV64-NEXT: mv a0, a1
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; RV64-NEXT: bgez a3, .LBB9_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: mv a0, a2
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; RV64-NEXT: .LBB9_2:
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; RV64-NEXT: ret
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%sh = ashr i32 %input, 31
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%c = icmp ne i32 %sh, -1
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%s = select i1 %c, i32 %a, i32 %b
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ret i32 %s
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}
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define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
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; RV32-LABEL: oneusecmp:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a3, a0, 31
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; RV32-NEXT: xori a3, a3, 127
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; RV32-NEXT: bltz a0, .LBB10_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: mv a2, a1
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; RV32-NEXT: .LBB10_2:
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; RV32-NEXT: add a0, a3, a2
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; RV32-NEXT: ret
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;
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; RV64-LABEL: oneusecmp:
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; RV64: # %bb.0:
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; RV64-NEXT: sext.w a3, a0
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; RV64-NEXT: sraiw a0, a0, 31
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; RV64-NEXT: xori a0, a0, 127
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; RV64-NEXT: bltz a3, .LBB10_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: mv a2, a1
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; RV64-NEXT: .LBB10_2:
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; RV64-NEXT: addw a0, a0, a2
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; RV64-NEXT: ret
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%c = icmp sle i32 %a, -1
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%s = select i1 %c, i32 -128, i32 127
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%s2 = select i1 %c, i32 %d, i32 %b
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%x = add i32 %s, %s2
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ret i32 %x
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}
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define i32 @xor_branch_imm_ret(i32 %x) nounwind {
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; RV32-LABEL: xor_branch_imm_ret:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: xori a0, a0, -1365
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; RV32-NEXT: beqz a0, .LBB11_2
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; RV32-NEXT: # %bb.1: # %if.then
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; RV32-NEXT: ret
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; RV32-NEXT: .LBB11_2: # %if.end
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: call abort
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;
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; RV64-LABEL: xor_branch_imm_ret:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: xori a0, a0, -1365
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; RV64-NEXT: sext.w a1, a0
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; RV64-NEXT: beqz a1, .LBB11_2
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; RV64-NEXT: # %bb.1: # %if.then
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; RV64-NEXT: ret
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; RV64-NEXT: .LBB11_2: # %if.end
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: call abort
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entry:
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%cmp.not = icmp eq i32 %x, -1365
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br i1 %cmp.not, label %if.end, label %if.then
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if.then:
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%xor = xor i32 %x, -1365
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ret i32 %xor
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if.end:
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tail call void @abort() #2
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unreachable
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}
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define i32 @xor_branch_ret(i32 %x) nounwind {
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; RV32-LABEL: xor_branch_ret:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a1, 1
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; RV32-NEXT: slli a1, a1, 11
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; RV32-NEXT: beq a0, a1, .LBB12_2
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; RV32-NEXT: # %bb.1: # %if.then
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; RV32-NEXT: xor a0, a0, a1
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; RV32-NEXT: ret
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; RV32-NEXT: .LBB12_2: # %if.end
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: call abort
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;
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; RV64-LABEL: xor_branch_ret:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: li a1, 1
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; RV64-NEXT: slli a1, a1, 11
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; RV64-NEXT: sext.w a2, a0
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; RV64-NEXT: beq a2, a1, .LBB12_2
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; RV64-NEXT: # %bb.1: # %if.then
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; RV64-NEXT: xor a0, a0, a1
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; RV64-NEXT: ret
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; RV64-NEXT: .LBB12_2: # %if.end
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: call abort
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entry:
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%cmp.not = icmp eq i32 %x, 2048
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br i1 %cmp.not, label %if.end, label %if.then
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if.then:
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%xor = xor i32 %x, 2048
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ret i32 %xor
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if.end:
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tail call void @abort() #2
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unreachable
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}
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declare void @abort()
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