48b6f4a182
It was relying on the fact that vsetvlis have side effects to prevent reordering, but #91319 proposes to remove the side effects. This reworks it to use volatile loads and stores instead.
59 lines
2.5 KiB
LLVM
59 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -target-abi=lp64 \
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; RUN: -verify-machineinstrs < %s \
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; RUN: | FileCheck %s
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define void @spill_half(ptr) nounwind {
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; CHECK-LABEL: spill_half:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: flh fa5, 0(a0)
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; CHECK-NEXT: fsh fa5, 14(sp) # 2-byte Folded Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: flh fa5, 14(sp) # 2-byte Folded Reload
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; CHECK-NEXT: fsh fa5, 0(a0)
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%2 = load volatile half, ptr %0
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call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
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store volatile half %2, ptr %0
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ret void
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}
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define void @spill_float(ptr) nounwind {
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; CHECK-LABEL: spill_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: flw fa5, 0(a0)
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; CHECK-NEXT: fsw fa5, 12(sp) # 4-byte Folded Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: flw fa5, 12(sp) # 4-byte Folded Reload
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; CHECK-NEXT: fsw fa5, 0(a0)
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%2 = load volatile float, ptr %0
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call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
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store volatile float %2, ptr %0
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ret void
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}
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define void @spill_double(ptr) nounwind {
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; CHECK-LABEL: spill_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: fld fa5, 0(a0)
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; CHECK-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: fld fa5, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: fsd fa5, 0(a0)
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%2 = load volatile double, ptr %0
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call void asm sideeffect "", "~{f0_d},~{f1_d},~{f2_d},~{f3_d},~{f4_d},~{f5_d},~{f6_d},~{f7_d},~{f8_d},~{f9_d},~{f10_d},~{f11_d},~{f12_d},~{f13_d},~{f14_d},~{f15_d},~{f16_d},~{f17_d},~{f18_d},~{f19_d},~{f20_d},~{f21_d},~{f22_d},~{f23_d},~{f24_d},~{f25_d},~{f26_d},~{f27_d},~{f28_d},~{f29_d},~{f30_d},~{f31_d}"()
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store volatile double %2, ptr %0
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ret void
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}
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