86eff6be68
This change adjusts the cost modeling used when the target does not have a schedule model with individual instruction latencies. After this change, we use the default latency information available from TargetSchedule. The default latency information essentially ends up treating most instructions as latency 1, with a few "expensive" ones getting a higher cost. Previously, we unconditionally applied the first legal pattern - without any consideration of profitability. As a result, this change both prevents some patterns being applied, and changes which patterns are exercised. (i.e. previously the first pattern was applied, afterwards, maybe the second one is because the first wasn't profitable.) The motivation here is two fold. First, this brings the default behavior in line with the behavior when -mcpu or -mtune is specified. This improves test coverage, and generally makes it less likely we will have bad surprises when providing more information to the compiler. Second, this enables some reassociation for ILP by default. Despite being unconditionally enabled, the prior code tended to "reassociate" repeatedly through an entire chain and simply moving the first operand to the end. The result was still a serial chain, just a different one. With this change, one of the intermediate transforms is unprofitable and we end up with a partially flattened tree. Note that the resulting code diffs show significant room for improvement in the basic algorithm. I am intentionally excluding those from this patch. For the test diffs, I don't seen any concerning regressions. I took a fairly close look at the RISCV ones, but only skimmed the x86 (particularly vector x86) changes. Differential Revision: https://reviews.llvm.org/D141017
194 lines
5.3 KiB
LLVM
194 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
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; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV32IZbb
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; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefix=RV64IZbb
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declare i4 @llvm.usub.sat.i4(i4, i4)
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declare i8 @llvm.usub.sat.i8(i8, i8)
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declare i16 @llvm.usub.sat.i16(i16, i16)
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declare i32 @llvm.usub.sat.i32(i32, i32)
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declare i64 @llvm.usub.sat.i64(i64, i64)
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define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
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; RV32I-LABEL: func:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a1, a0, a1
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: subw a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y);
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ret i32 %tmp;
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: func2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sltu a4, a0, a2
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; RV32I-NEXT: sub a3, a1, a3
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; RV32I-NEXT: sub a3, a3, a4
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; RV32I-NEXT: sub a2, a0, a2
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; RV32I-NEXT: beq a3, a1, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a0, a1, a3
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; RV32I-NEXT: j .LBB1_3
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: sltu a0, a0, a2
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; RV32I-NEXT: .LBB1_3:
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; RV32I-NEXT: addi a1, a0, -1
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; RV32I-NEXT: and a0, a1, a2
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func2:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: sltu a4, a0, a2
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; RV32IZbb-NEXT: sub a3, a1, a3
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; RV32IZbb-NEXT: sub a3, a3, a4
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; RV32IZbb-NEXT: sub a2, a0, a2
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; RV32IZbb-NEXT: beq a3, a1, .LBB1_2
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; RV32IZbb-NEXT: # %bb.1:
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; RV32IZbb-NEXT: sltu a0, a1, a3
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; RV32IZbb-NEXT: j .LBB1_3
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; RV32IZbb-NEXT: .LBB1_2:
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; RV32IZbb-NEXT: sltu a0, a0, a2
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; RV32IZbb-NEXT: .LBB1_3:
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; RV32IZbb-NEXT: addi a1, a0, -1
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; RV32IZbb-NEXT: and a0, a1, a2
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; RV32IZbb-NEXT: and a1, a1, a3
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func2:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y);
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ret i64 %tmp;
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}
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define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; RV32I-LABEL: func16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func16:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func16:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
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ret i16 %tmp;
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}
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define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; RV32I-LABEL: func8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func8:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func8:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
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ret i8 %tmp;
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}
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define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
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; RV32I-LABEL: func3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: func3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sub a1, a0, a1
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; RV64I-NEXT: sltu a0, a0, a1
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32IZbb-LABEL: func3:
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; RV32IZbb: # %bb.0:
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; RV32IZbb-NEXT: maxu a0, a0, a1
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; RV32IZbb-NEXT: sub a0, a0, a1
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; RV32IZbb-NEXT: ret
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;
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; RV64IZbb-LABEL: func3:
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; RV64IZbb: # %bb.0:
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; RV64IZbb-NEXT: maxu a0, a0, a1
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; RV64IZbb-NEXT: sub a0, a0, a1
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; RV64IZbb-NEXT: ret
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%tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y);
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ret i4 %tmp;
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}
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