6441df3b59
Implement XCVmac intrinsics for CV32E40P according to the specification. This commit is part of a patch-set to upstream the vendor specific extensions of CV32E40P that need LLVM intrinsics to implement Clang builtins. Contributors: @CharKeaney, @ChunyuLiao, @jeremybennett, @lewis-revill, @NandniJamnadas, @PaoloS02, @serkm, @simonpcook, @xingmingjie.
212 lines
5.7 KiB
LLVM
212 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+xcvmac -verify-machineinstrs < %s \
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; RUN: | FileCheck %s
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declare i32 @llvm.riscv.cv.mac.mac(i32, i32, i32)
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define i32 @test.mac(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.mac:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mac a2, a0, a1
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.mac(i32 %a, i32 %b, i32 %c)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.msu(i32, i32, i32)
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define i32 @test.msu(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.msu:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.msu a2, a0, a1
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.msu(i32 %a, i32 %b, i32 %c)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.muluN(i32, i32, i32)
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define i32 @test.muluN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.muluN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulun a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.muluN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.mulhhuN(i32, i32, i32)
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define i32 @test.mulhhuN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.mulhhuN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulhhun a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.mulhhuN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.mulsN(i32, i32, i32)
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define i32 @test.mulsN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.mulsN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulsn a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.mulsN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.mulhhsN(i32, i32, i32)
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define i32 @test.mulhhsN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.mulhhsN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulhhsn a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.mulhhsN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.muluRN(i32, i32, i32)
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define i32 @test.muluRN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.muluRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulurn a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.muluRN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.mulhhuRN(i32, i32, i32)
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define i32 @test.mulhhuRN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.mulhhuRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulhhurn a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.mulhhuRN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.mulsRN(i32, i32, i32)
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define i32 @test.mulsRN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.mulsRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulsrn a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.mulsRN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.mulhhsRN(i32, i32, i32)
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define i32 @test.mulhhsRN(i32 %a, i32 %b) {
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; CHECK-LABEL: test.mulhhsRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.mulhhsrn a0, a0, a1, 5
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.mulhhsRN(i32 %a, i32 %b, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.macuN(i32, i32, i32, i32)
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define i32 @test.macuN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.macuN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.macun a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.macuN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.machhuN(i32, i32, i32, i32)
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define i32 @test.machhuN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.machhuN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.machhun a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.machhuN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.macsN(i32, i32, i32, i32)
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define i32 @test.macsN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.macsN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.macsn a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.macsN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.machhsN(i32, i32, i32, i32)
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define i32 @test.machhsN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.machhsN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.machhsn a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.machhsN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.macuRN(i32, i32, i32, i32)
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define i32 @test.macuRN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.macuRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.macurn a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.macuRN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.machhuRN(i32, i32, i32, i32)
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define i32 @test.machhuRN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.machhuRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.machhurn a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.machhuRN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.macsRN(i32, i32, i32, i32)
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define i32 @test.macsRN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.macsRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.macsrn a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.macsRN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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declare i32 @llvm.riscv.cv.mac.machhsRN(i32, i32, i32, i32)
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define i32 @test.machhsRN(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test.machhsRN:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cv.machhsrn a2, a0, a1, 5
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: ret
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%1 = call i32 @llvm.riscv.cv.mac.machhsRN(i32 %a, i32 %b, i32 %c, i32 5)
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ret i32 %1
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}
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