c00b04a7e0
Generate QC_INSB/QC_INSBI from `or (and X, MaskImm), OrImm` iff the value being inserted only sets known zero bits. This is based on a similar DAG to DAG transform done in `AArch64`.
347 lines
9.5 KiB
LLVM
347 lines
9.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32IXQCIBM
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm,+zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32IXQCIBMZBS
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define i32 @test_ori(i32 %a) nounwind {
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; RV32I-LABEL: test_ori:
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; RV32I: # %bb.0:
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; RV32I-NEXT: ori a0, a0, 511
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test_ori:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: ori a0, a0, 511
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test_ori:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: ori a0, a0, 511
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; RV32IXQCIBMZBS-NEXT: ret
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%or = or i32 %a, 511
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ret i32 %or
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}
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define i32 @test_insbi_mask(i32 %a) nounwind {
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; RV32I-LABEL: test_insbi_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test_insbi_mask:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 16, 0
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test_insbi_mask:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, -1, 16, 0
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; RV32IXQCIBMZBS-NEXT: ret
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%or = or i32 %a, 65535
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ret i32 %or
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}
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define i32 @test_insbi_mask_mv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: test_insbi_mask_mv:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, 16
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test_insbi_mask_mv:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: mv a0, a1
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; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 16, 0
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test_insbi_mask_mv:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: mv a0, a1
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, -1, 16, 0
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; RV32IXQCIBMZBS-NEXT: ret
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%or = or i32 %b, 65535
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ret i32 %or
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}
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define i32 @test_insbi_shifted_mask(i32 %a) nounwind {
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; RV32I-LABEL: test_insbi_shifted_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 15
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test_insbi_shifted_mask:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 4, 12
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test_insbi_shifted_mask:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, -1, 4, 12
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; RV32IXQCIBMZBS-NEXT: ret
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%or = or i32 %a, 61440
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ret i32 %or
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}
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define i32 @test_insbi_shifted_mask_multiple_uses(i32 %a) nounwind {
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; RV32I-LABEL: test_insbi_shifted_mask_multiple_uses:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 15
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; RV32I-NEXT: or a1, a0, a1
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; RV32I-NEXT: addi a0, a0, 10
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; RV32I-NEXT: xor a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test_insbi_shifted_mask_multiple_uses:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: lui a1, 15
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; RV32IXQCIBM-NEXT: or a1, a1, a0
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; RV32IXQCIBM-NEXT: addi a0, a0, 10
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; RV32IXQCIBM-NEXT: xor a0, a0, a1
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test_insbi_shifted_mask_multiple_uses:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: lui a1, 15
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; RV32IXQCIBMZBS-NEXT: or a1, a1, a0
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; RV32IXQCIBMZBS-NEXT: addi a0, a0, 10
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; RV32IXQCIBMZBS-NEXT: xor a0, a0, a1
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; RV32IXQCIBMZBS-NEXT: ret
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%or = or i32 %a, 61440
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%add = add i32 %a, 10
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%xor = xor i32 %or, %add
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ret i32 %xor
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}
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define i32 @test_single_bit_set(i32 %a) nounwind {
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; RV32I-LABEL: test_single_bit_set:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test_single_bit_set:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, -1, 1, 12
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test_single_bit_set:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: bseti a0, a0, 12
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; RV32IXQCIBMZBS-NEXT: ret
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%or = or i32 %a, 4096
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ret i32 %or
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}
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; Tests for INSB(I) generation from OR and AND
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define i32 @test1(i32 %a) {
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; RV32I-LABEL: test1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, -16
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; RV32I-NEXT: addi a0, a0, 5
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test1:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, 5, 4, 0
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test1:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 5, 4, 0
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i32 %a, -16 ; 0xfffffff0
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%2 = or i32 %1, 5 ; 0x00000005
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ret i32 %2
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}
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define i32 @test2(i32 %a) {
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; RV32I-LABEL: test2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1033216
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: lui a1, 10240
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test2:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, 10, 4, 22
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test2:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 10, 4, 22
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i32 %a, -62914561 ; 0xfc3fffff
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%2 = or i32 %1, 41943040 ; 0x02800000
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ret i32 %2
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}
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define i64 @test3(i64 %a) {
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; RV32I-LABEL: test3:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, -8
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; RV32I-NEXT: addi a0, a0, 5
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test3:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, 5, 3, 0
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test3:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 5, 3, 0
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i64 %a, -8 ; 0xfffffffffffffff8
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%2 = or i64 %1, 5 ; 0x0000000000000005
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ret i64 %2
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}
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define i64 @test4(i64 %a) {
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; RV32I-LABEL: test4:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, -255
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; RV32I-NEXT: addi a0, a0, 18
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test4:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, 9, 7, 1
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test4:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 9, 7, 1
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i64 %a, -255 ; 0xffffffffffffff01
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%2 = or i64 %1, 18 ; 0x0000000000000012
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ret i64 %2
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}
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define i32 @test5(i32 %a) {
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; RV32I-LABEL: test5:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, -16
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; RV32I-NEXT: addi a0, a0, 6
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test5:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: qc.insbi a0, 6, 4, 0
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test5:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: qc.insbi a0, 6, 4, 0
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i32 %a, 4294967280 ; 0xfffffff0
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%2 = or i32 %1, 6 ; 0x00000006
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ret i32 %2
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}
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define i32 @test6(i32 %a) {
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; RV32I-LABEL: test6:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048320
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: lui a1, 182
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; RV32I-NEXT: addi a1, a1, -1326
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test6:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: lui a1, 182
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; RV32IXQCIBM-NEXT: addi a1, a1, -1326
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; RV32IXQCIBM-NEXT: qc.insb a0, a1, 20, 0
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test6:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: lui a1, 182
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; RV32IXQCIBMZBS-NEXT: addi a1, a1, -1326
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; RV32IXQCIBMZBS-NEXT: qc.insb a0, a1, 20, 0
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i32 %a, 4293918720 ; 0xfff00000
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%2 = or i32 %1, 744146 ; 0x000b5ad2
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ret i32 %2
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}
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define i32 @test7(i32 %a) {
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; RV32I-LABEL: test7:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048320
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; RV32I-NEXT: addi a1, a1, 1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: lui a1, 182
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; RV32I-NEXT: addi a1, a1, -1326
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test7:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: lui a1, 91
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; RV32IXQCIBM-NEXT: addi a1, a1, -663
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; RV32IXQCIBM-NEXT: qc.insb a0, a1, 19, 1
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test7:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: lui a1, 91
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; RV32IXQCIBMZBS-NEXT: addi a1, a1, -663
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; RV32IXQCIBMZBS-NEXT: qc.insb a0, a1, 19, 1
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i32 %a, 4293918721 ; 0xfff00001
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%2 = or i32 %1, 744146 ; 0x000b5ad2
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ret i32 %2
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}
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define i64 @test8(i64 %a) {
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; RV32I-LABEL: test8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 1044480
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; RV32I-NEXT: zext.b a0, a0
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; RV32I-NEXT: and a1, a1, a2
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; RV32I-NEXT: lui a2, 496944
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: lui a2, 9
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; RV32I-NEXT: addi a2, a2, -170
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV32IXQCIBM-LABEL: test8:
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; RV32IXQCIBM: # %bb.0:
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; RV32IXQCIBM-NEXT: lui a2, 1941
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; RV32IXQCIBM-NEXT: addi a2, a2, 768
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; RV32IXQCIBM-NEXT: qc.insb a0, a2, 24, 8
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; RV32IXQCIBM-NEXT: lui a2, 9
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; RV32IXQCIBM-NEXT: addi a2, a2, -170
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; RV32IXQCIBM-NEXT: qc.insb a1, a2, 24, 0
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; RV32IXQCIBM-NEXT: ret
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;
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; RV32IXQCIBMZBS-LABEL: test8:
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; RV32IXQCIBMZBS: # %bb.0:
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; RV32IXQCIBMZBS-NEXT: lui a2, 1941
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; RV32IXQCIBMZBS-NEXT: addi a2, a2, 768
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; RV32IXQCIBMZBS-NEXT: qc.insb a0, a2, 24, 8
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; RV32IXQCIBMZBS-NEXT: lui a2, 9
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; RV32IXQCIBMZBS-NEXT: addi a2, a2, -170
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; RV32IXQCIBMZBS-NEXT: qc.insb a1, a2, 24, 0
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; RV32IXQCIBMZBS-NEXT: ret
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%1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff
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%2 = or i64 %1, 157601565442048 ; 0x00008f5679530000
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ret i64 %2
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}
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