40460a5cf7
This patch adds basic instruction selection patterns for generating the 48 bit load/store instructions that are a part of the Qualcomm uC Xqcilo vendor extension.
144 lines
3.6 KiB
LLVM
144 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32IXQCILO
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define i32 @lb_ri(i8* %a) {
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; RV32I-LABEL: lb_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 2
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lb a0, 1808(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: lb_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.lb a0, 10000(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i8, i8* %a, i32 10000
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%2 = load i8, i8* %1
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%3 = sext i8 %2 to i32
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ret i32 %3
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}
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define i32 @lbu_ri(i8* %a) {
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; RV32I-LABEL: lbu_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048574
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lbu a0, 192(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: lbu_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.lbu a0, -8000(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i8, i8* %a, i32 -8000
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%2 = load i8, i8* %1
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%3 = zext i8 %2 to i32
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ret i32 %3
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}
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define i32 @lh_ri(i16* %a) {
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; RV32I-LABEL: lh_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 11
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lhu a0, -612(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: lh_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.lhu a0, 44444(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i16, i16* %a, i32 22222
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%2 = load i16, i16* %1
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%3 = zext i16 %2 to i32
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ret i32 %3
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}
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define i32 @lhu_ri(i16* %a) {
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; RV32I-LABEL: lhu_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048570
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lhu a0, 120(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: lhu_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.lhu a0, -24456(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i16, i16* %a, i32 -12228
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%2 = load i16, i16* %1
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%3 = zext i16 %2 to i32
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ret i32 %3
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}
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define i32 @lw_ri(i32* %a) {
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; RV32I-LABEL: lw_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: lw a0, 1953(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: lw_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.lw a0, 4000(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i32, i32* %a, i32 1000
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%2 = load i32, i32* %1
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ret i32 %2
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}
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define void @sb_ri(i8* %a, i8 %b) {
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; RV32I-LABEL: sb_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 2
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: sb a1, 1808(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: sb_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.sb a1, 10000(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i8, i8* %a, i32 10000
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store i8 %b, i8* %1
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ret void
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}
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define void @sh_ri(i16* %a, i16 %b) {
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; RV32I-LABEL: sh_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 11
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: sh a1, -612(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: sh_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.sh a1, 44444(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i16, i16* %a, i32 22222
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store i16 %b, i16* %1
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ret void
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}
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define void @sw_ri(i32* %a, i32 %b) {
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; RV32I-LABEL: sw_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: sw a1, 1953(a0)
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; RV32I-NEXT: ret
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;
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; RV32IXQCILO-LABEL: sw_ri:
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; RV32IXQCILO: # %bb.0:
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; RV32IXQCILO-NEXT: qc.e.sw a1, 4000(a0)
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; RV32IXQCILO-NEXT: ret
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%1 = getelementptr i32, i32* %a, i32 1000
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store i32 %b, i32* %1
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ret void
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}
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