7faf1a0868
This patch adds a pass that provides workarounds for the errata described in GRLIB-TN-0009, GRLIB-TN-0010, GRLIB-TN-0011, GRLIB-TN-0012, and GRLIB-TN-0013, that are applicable to the GR712RC and UT700. The documents are available for download from here: https://www.gaisler.com/index.php/information/app-tech-notes The pass will detect certain sensitive instruction sequences and prevent them from occurring by inserting NOP instruction. Below is an overview of each of the workarounds. A similar implementation is available in GCC. GRLIB-TN-0009: * Insert NOPs to prevent the sequence (stb/sth/st/stf) -> (single non-store/load instruction) -> (any store) * Insert NOPs to prevent the sequence (std/stdf) -> (any store) GRLIB-TN-0010: * Insert a NOP between load instruction and atomic instruction (swap and casa). * Insert a NOP at branch target if load in delay slot and atomic instruction at branch target. * Do not allow functions to begin with atomic instruction. GRLIB-TN-0011: * Insert .p2align 4 before atomic instructions (swap and casa). GRLIB-TN-0012: * Place a NOP at the branch target of an integer branch if it is a floating-point operation or a floating-point branch. GRLIB-TN-0013: * Prevent (div/sqrt) instructions in the delay slot. * Insert NOPs to prevent the sequence (div/sqrt) -> (two or three floating point operations or loads) -> (div/sqrt). * Do not insert NOPs if any of the floating point operations have a dependency on the destination register of the first (div/sqrt). * Do not insert NOPs if one of the floating point operations is a (div/sqrt). * Insert NOPs to prevent (div/sqrt) followed by a branch.
27 lines
586 B
LLVM
27 lines
586 B
LLVM
; RUN: llc < %s -mtriple=sparc -mattr=fix-tn0011,hasleoncasa | FileCheck %s
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; CHECK: .p2align 4
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; CHECK-NEXT: casa
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define i32 @test_casarr(i32* %p, i32 %v) {
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entry:
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%0 = atomicrmw nand i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK: .p2align 4
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; CHECK-NEXT: swap
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define i32 @test_swaprr(i32* %p, i32 %v) {
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entry:
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%0 = atomicrmw xchg i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK: .p2align 4
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; CHECK-NEXT: swap
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define i32 @test_swapri(i32* %p, i32 %v) {
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entry:
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%1 = getelementptr inbounds i32, ptr %p, i32 1
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%2 = atomicrmw xchg ptr %1, i32 %v seq_cst, align 4
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ret i32 %2
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}
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