ee13638362
Since e39f6c1844fab59c638d8059a6cf139adb42279a opt will infer the correct datalayout when given a triple. Avoid explicitly specifying it in tests that depend on the AMDGPU target being present to avoid the string becoming out of sync with the TargetInfo value. Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg were updated to ensure that tests for non-target-specific passes that happen to use the AMDGPU layout still pass when building with a limited set of targets. Reviewed By: shiltian, arsenm Pull Request: https://github.com/llvm/llvm-project/pull/137921
135 lines
6.2 KiB
LLVM
135 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -loop-reduce %s | FileCheck %s
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; Test for assert resulting from inconsistent isLegalAddressingMode
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; answers when the address space was dropped from the query.
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%0 = type { i32, double, i32, float }
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define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type() #0 {
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; CHECK-LABEL: define amdgpu_kernel void @lsr_crash_preserve_addrspace_unknown_type(
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; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[BB:.*]]:
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; CHECK-NEXT: br label %[[BB1:.*]]
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; CHECK: [[BB1]]:
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; CHECK-NEXT: [[TMP:%.*]] = phi ptr addrspace(3) [ undef, %[[BB]] ], [ [[TMP18:%.*]], %[[BB17:.*]] ]
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; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 8
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; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr addrspace(3) [[SCEVGEP1]], align 8
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; CHECK-NEXT: br label %[[BB4:.*]]
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; CHECK: [[BB4]]:
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; CHECK-NEXT: br i1 false, label %[[BB8:.*]], label %[[BB5:.*]]
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; CHECK: [[BB5]]:
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; CHECK-NEXT: unreachable
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; CHECK: [[BB8]]:
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; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(3) [[TMP]], align 4
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 0, [[TMP10]]
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; CHECK-NEXT: br i1 [[TMP11]], label %[[BB12:.*]], label %[[BB17]]
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; CHECK: [[BB12]]:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP]], i32 16
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; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(3) [[SCEVGEP]], align 4
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; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 0, [[TMP14]]
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; CHECK-NEXT: br i1 [[TMP15]], label %[[BB16:.*]], label %[[BB17]]
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; CHECK: [[BB16]]:
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; CHECK-NEXT: unreachable
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; CHECK: [[BB17]]:
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; CHECK-NEXT: [[TMP18]] = getelementptr inbounds [[TMP0:%.*]], ptr addrspace(3) [[TMP]], i64 2
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; CHECK-NEXT: br label %[[BB1]]
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;
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bb:
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br label %bb1
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bb1: ; preds = %bb17, %bb
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%tmp = phi ptr addrspace(3) [ undef, %bb ], [ %tmp18, %bb17 ]
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%tmp2 = getelementptr inbounds %0, ptr addrspace(3) %tmp, i64 0, i32 1
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%tmp3 = load double, ptr addrspace(3) %tmp2, align 8
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br label %bb4
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bb4: ; preds = %bb1
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br i1 false, label %bb8, label %bb5
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bb5: ; preds = %bb4
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unreachable
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bb8: ; preds = %bb4
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%tmp10 = load i32, ptr addrspace(3) %tmp, align 4
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%tmp11 = icmp eq i32 0, %tmp10
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br i1 %tmp11, label %bb12, label %bb17
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bb12: ; preds = %bb8
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%tmp13 = getelementptr inbounds %0, ptr addrspace(3) %tmp, i64 0, i32 2
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%tmp14 = load i32, ptr addrspace(3) %tmp13, align 4
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%tmp15 = icmp eq i32 0, %tmp14
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br i1 %tmp15, label %bb16, label %bb17
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bb16: ; preds = %bb12
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unreachable
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bb17: ; preds = %bb12, %bb8
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%tmp18 = getelementptr inbounds %0, ptr addrspace(3) %tmp, i64 2
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br label %bb1
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}
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define void @lsr_crash_preserve_addrspace_unknown_type2(ptr addrspace(5) %array, ptr addrspace(3) %array2) {
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; CHECK-LABEL: define void @lsr_crash_preserve_addrspace_unknown_type2(
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; CHECK-SAME: ptr addrspace(5) [[ARRAY:%.*]], ptr addrspace(3) [[ARRAY2:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[FOR_BODY:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[J:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_INC:.*]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: [[IDX:%.*]] = getelementptr i8, ptr addrspace(5) [[ARRAY]], i32 [[J]]
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; CHECK-NEXT: [[IDX1:%.*]] = getelementptr i8, ptr addrspace(3) [[ARRAY2]], i32 [[J]]
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; CHECK-NEXT: [[T:%.*]] = getelementptr i8, ptr addrspace(5) [[ARRAY]], i32 [[J]]
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; CHECK-NEXT: [[N8:%.*]] = load i8, ptr addrspace(5) [[T]], align 4
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; CHECK-NEXT: [[N7:%.*]] = getelementptr i8, ptr addrspace(5) [[T]], i32 42
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; CHECK-NEXT: [[N9:%.*]] = load i8, ptr addrspace(5) [[N7]], align 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[J]], 42
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; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN17:.*]], label %[[FOR_INC]]
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; CHECK: [[IF_THEN17]]:
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; CHECK-NEXT: call void @llvm.memcpy.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false)
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; CHECK-NEXT: call void @llvm.memmove.p5.p3.i64(ptr addrspace(5) [[IDX]], ptr addrspace(3) [[IDX1]], i64 42, i1 false)
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; CHECK-NEXT: call void @llvm.memset.p5.i64(ptr addrspace(5) [[IDX]], i8 42, i64 42, i1 false)
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; CHECK-NEXT: br label %[[FOR_INC]]
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; CHECK: [[FOR_INC]]:
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i1 [[CMP]], true
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; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[J]], 1
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; CHECK-NEXT: br i1 [[EXITCOND]], label %[[END:.*]], label %[[FOR_BODY]]
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; CHECK: [[END]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.inc
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%j = phi i32 [ %add, %for.inc ], [ 0, %entry ]
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%idx = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j
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%idx1 = getelementptr inbounds i8, ptr addrspace(3) %array2, i32 %j
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%t = getelementptr inbounds i8, ptr addrspace(5) %array, i32 %j
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%n8 = load i8, ptr addrspace(5) %t, align 4
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%n7 = getelementptr inbounds i8, ptr addrspace(5) %t, i32 42
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%n9 = load i8, ptr addrspace(5) %n7, align 4
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%cmp = icmp sgt i32 %j, 42
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%add = add nuw nsw i32 %j, 1
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br i1 %cmp, label %if.then17, label %for.inc
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if.then17: ; preds = %for.body
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call void @llvm.memcpy.p5.p5.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false)
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call void @llvm.memmove.p5.p5.i64(ptr addrspace(5) %idx, ptr addrspace(3) %idx1, i64 42, i1 false)
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call void @llvm.memset.p5.i64(ptr addrspace(5) %idx, i8 42, i64 42, i1 false)
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then17
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%exitcond = icmp eq i1 %cmp, 1
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br i1 %exitcond, label %end, label %for.body
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end: ; preds = %for.inc
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ret void
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}
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declare void @llvm.memcpy.p5.p5.i64(ptr addrspace(5), ptr addrspace(3), i64, i1)
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declare void @llvm.memmove.p5.p5.i64(ptr addrspace(5), ptr addrspace(3), i64, i1)
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declare void @llvm.memset.p5.i64(ptr addrspace(5), i8, i64, i1)
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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