llvm-project

History

[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context (#147664 )

Add LLVM Context to getOptimalMemOpType and findOptimalMemOpLowering. So
that we can use EVT::getVectorVT to generate EVT type in
getOptimalMemOpType.

Related to [#146673](https://github.com/llvm/llvm-project/pull/146673).

2025-07-10 11:11:09 +08:00

CMakeLists.txt

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358 )

2025-04-06 13:14:37 +03:00

DAGCombiner.cpp

[DAG] Fold insert_subvector (splat X), (splat X), N2 - > splat X (#147380 )

2025-07-08 08:50:01 -07:00

FastISel.cpp

[RemoveDIs][NFC] Remove dbg intrinsic handling code from SelectionDAG ISel (#144702 )

2025-06-18 16:04:18 +01:00

FunctionLoweringInfo.cpp

[RemoveDIs][NFC] Remove dbg intrinsic handling code from SelectionDAG ISel (#144702 )

2025-06-18 16:04:18 +01:00

InstrEmitter.cpp

[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637 )

2025-07-02 09:44:54 -07:00

InstrEmitter.h

…

LegalizeDAG.cpp

DAG: Remove dead declaration of ExpandSinCosLibCall (#147673 )

2025-07-09 18:47:49 +09:00

LegalizeFloatTypes.cpp

DAG: Fall back to separate sin and cos when softening sincos (#147468 )

2025-07-09 01:52:46 +09:00

LegalizeIntegerTypes.cpp

[LegalizeTypes] Preserve disjoint flag when expanding OR. (#147640 )

2025-07-09 14:15:42 -07:00

LegalizeTypes.cpp

[CodeGen] Use llvm::append_range (NFC) (#135567 )

2025-04-13 16:36:03 -07:00

LegalizeTypes.h

DAG: Fall back to separate sin and cos when softening sincos (#147468 )

2025-07-09 01:52:46 +09:00

LegalizeTypesGeneric.cpp

[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930 )

2025-05-16 09:37:02 -07:00

LegalizeVectorOps.cpp

[LLVM][CodeGen][SVE] Add isel for bfloat unordered reductions. (#143540 )

2025-06-20 11:46:25 +01:00

LegalizeVectorTypes.cpp

[SelectionDAG][RISCV] Add support for splitting vp.splice (#145184 )

2025-06-23 08:55:13 -07:00

MatchContext.h

…

ResourcePriorityQueue.cpp

[llvm] Use llvm::fill instead of std::fill(NFC) (#146911 )

2025-07-04 14:10:28 +08:00

ScheduleDAGFast.cpp

[CodeGen] Use range-based for loops (NFC) (#138488 )

2025-05-05 10:08:49 -07:00

ScheduleDAGRRList.cpp

[llvm] Use llvm::fill instead of std::fill(NFC) (#146911 )

2025-07-04 14:10:28 +08:00

ScheduleDAGSDNodes.cpp

[SelectionDAG] Use Register and MCRegister. NFC

2025-03-02 22:33:25 -08:00

ScheduleDAGSDNodes.h

[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934 )

2025-01-23 09:16:09 +00:00

ScheduleDAGVLIW.cpp

[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934 )

2025-01-23 09:16:09 +00:00

SDNodeDbgValue.h

[llvm] Use llvm::copy (NFC) (#137470 )

2025-04-26 15:50:38 -07:00

SDNodeInfo.cpp

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358 )

2025-04-06 13:14:37 +03:00

SelectionDAG.cpp

[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context (#147664 )

2025-07-10 11:11:09 +08:00

SelectionDAGAddressAnalysis.cpp

[AMDGPU][SDAG] Handle ISD::PTRADD in SelectionDAGAddressAnalysis (#142778 )

2025-06-26 09:47:46 +02:00

SelectionDAGBuilder.cpp

[SDAG] Prefer scalar for prefix of vector GEP expansion (#146719 )

2025-07-02 18:16:27 -07:00

SelectionDAGBuilder.h

[RemoveDIs][NFC] Remove dbg intrinsic handling code from SelectionDAG ISel (#144702 )

2025-06-18 16:04:18 +01:00

SelectionDAGDumper.cpp

[SDAG] Add partial_reduce_sumla node (#141267 )

2025-06-09 07:17:45 -07:00

SelectionDAGISel.cpp

[SelectionDAG] Correctly Mark Required Analyses (#147649 )

2025-07-08 21:40:29 -07:00

SelectionDAGPrinter.cpp

…

SelectionDAGTargetInfo.cpp

[SelectionDAG] Wire up -gen-sdnode-info TableGen backend (#125358 )

2025-04-06 13:14:37 +03:00

StatepointLowering.cpp

[CodeGen] Avoid repeated hash lookups (NFC) (#131722 )

2025-03-18 00:26:59 -07:00

StatepointLowering.h

…

TargetLowering.cpp

[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to take LLVM Context (#147664 )

2025-07-10 11:11:09 +08:00