d5666294e9
Ported hasAllNBitUsers to RISCV GISel side. Add GISelPredicate code to each of the 16,32, and 64 bit words. It allows for generation of optimized packw sequences along with other transparent narrowing operations. Included a few new .ll files to expand testing and limited the OptW pass Optimization to fewer options until GISel is ready for more code generation paths --------- Signed-off-by: Luke Quinn <quic_lquinn@quicinc.com>
53 lines
1.5 KiB
LLVM
53 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs -O0 < %s \
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; RUN: | FileCheck %s --check-prefixes=RV32,RV32-O0
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; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs -O0 < %s \
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; RUN: | FileCheck %s --check-prefixes=RV64,RV64-O0
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; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=RV32,RV32-OPT
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; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=RV64,RV64-OPT
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define i32 @constant_to_rhs(i32 %x) {
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; RV32-O0-LABEL: constant_to_rhs:
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; RV32-O0: # %bb.0:
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; RV32-O0-NEXT: mv a1, a0
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; RV32-O0-NEXT: li a0, 1
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; RV32-O0-NEXT: add a0, a0, a1
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; RV32-O0-NEXT: ret
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;
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; RV64-O0-LABEL: constant_to_rhs:
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; RV64-O0: # %bb.0:
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; RV64-O0-NEXT: mv a1, a0
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; RV64-O0-NEXT: li a0, 1
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; RV64-O0-NEXT: addw a0, a0, a1
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; RV64-O0-NEXT: sext.w a0, a0
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; RV64-O0-NEXT: ret
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;
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; RV32-OPT-LABEL: constant_to_rhs:
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; RV32-OPT: # %bb.0:
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; RV32-OPT-NEXT: addi a0, a0, 1
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; RV32-OPT-NEXT: ret
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;
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; RV64-OPT-LABEL: constant_to_rhs:
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; RV64-OPT: # %bb.0:
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; RV64-OPT-NEXT: addiw a0, a0, 1
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; RV64-OPT-NEXT: ret
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%a = add i32 1, %x
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ret i32 %a
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}
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define i32 @mul_to_shift(i32 %x) {
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; RV32-LABEL: mul_to_shift:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 2
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; RV32-NEXT: ret
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;
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; RV64-LABEL: mul_to_shift:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a0, a0, 2
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; RV64-NEXT: ret
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%a = mul i32 %x, 4
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ret i32 %a
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}
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