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llvm-project/llvm/test/CodeGen/RISCV/GlobalISel
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Shaoce SUN 7e8ff2afa9
[RISCV][GISel] Optimize +0.0 to use fcvt.d.w for s64 on rv32 (#153978) 
Resolve the TODO: on RV32, when constructing the double-precision
constant `+0.0` for `s64`, `BuildPairF64Pseudo` can be optimized to use
the `fcvt.d.w` instruction to generate the result directly.
2025-08-18 17:52:24 +00:00
..
instruction-select
[RISCV][GISel] Optimize +0.0 to use fcvt.d.w for s64 on rv32 (#153978)
2025-08-18 17:52:24 +00:00
irtranslator
[GISel] Introduce MIFlags::InBounds (#150900)
2025-07-30 13:01:23 +02:00
legalizer
[RISCV][GISel][NFC] Add MIR legalizer tests for G_UADDE (rv32 & rv64) (#152827)
2025-08-12 09:59:17 -07:00
regbankselect
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rvv
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add-imm.ll
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alu-roundtrip-rv64.ll
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alu-roundtrip.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
atomic-fence.ll
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atomic-load-store.ll
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bitmanip.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
calllowering-ret.ll
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calls.ll
[RISCV][GISel] Use the correct calling convention during call lowering (#142148)
2025-05-30 18:55:32 +02:00
combine-neg-abs.ll
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combine.ll
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combine.mir
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constantpool.ll
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constbarrier-rv32.ll
[MCP] Handle iterative simplification during forward copy prop (#140267)
2025-06-02 11:21:41 -07:00
constbarrier-rv64.ll
[MCP] Handle iterative simplification during forward copy prop (#140267)
2025-06-02 11:21:41 -07:00
div-by-constant.ll
[GlobalISel] Add computeNumSignBits for ASHR (#139503)
2025-07-21 10:23:26 +01:00
double-arith.ll
[RISCV][GISel] Optimize +0.0 to use fcvt.d.w for s64 on rv32 (#153978)
2025-08-18 17:52:24 +00:00
double-convert.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
double-fcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
double-intrinsics.ll
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double-zfa.ll
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float-arith.ll
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float-convert.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
float-fclass.ll
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float-fcmp.ll
[RISCV] Improve instruction selection for most significant bit extraction (#151687)
2025-08-14 09:59:43 +02:00
float-intrinsics.ll
[RISCV][ISel] Optimize setcc with mask test idioms (#147015)
2025-07-05 13:01:57 +08:00
float-zfa.ll
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fp128.ll
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fpr-gpr-copy-rv32.ll
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fpr-gpr-copy-rv64.ll
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freeze.ll
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gisel-commandline-option.ll
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half-zfa.ll
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iabs.ll
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irtranslator-calllowering.ll
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jumptable.ll
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knownbits-copy-crash.mir
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legalizer-info-validation.mir
[X86][GlobalISel] Added support for llvm.get.rounding (#147716)
2025-07-11 15:48:18 +02:00
libcalls.ll
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phi.ll
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riscv-unsupported.ll
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rotl-rotr.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv32zba.ll
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rv32zbb-zbkb.ll
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rv32zbb.ll
[MCP] Handle iterative simplification during forward copy prop (#140267)
2025-06-02 11:21:41 -07:00
rv32zbkb.ll
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rv64-double-convert.ll
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rv64-float-convert.ll
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rv64zba.ll
[RISCV] Fix copy/paste mistake in test comments. NFC
2025-05-19 15:49:41 -07:00
rv64zbb-zbkb.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
rv64zbb.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
rv64zbkb.ll
[RISCV] Convert LWU to LW if possible in RISCVOptWInstrs (#144703)
2025-07-21 11:48:33 +01:00
scalablevec-combiner-crash.ll
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scmp.ll
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shift.ll
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shifts.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00
stacksave-stackrestore.ll
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ucmp.ll
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vararg.ll
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663)
2025-06-02 22:24:50 +01:00
wide-scalar-shift-by-byte-multiple-legalization.ll
[RISCV] Add RISCV::SUBW to RISCVOptWInstrs::stripWSuffixes (#149071)
2025-07-20 09:59:41 +01:00