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llvm-project/llvm/test/CodeGen/RISCV/rv64zbs.ll
Alex Bradbury 3d2650bdeb
[RISCV] Use addi rather than addiw for immediates materialised by lui+addi(w) pairs when possible (#141663) 
The logic in RISCVMatInt would previously produce lui+addiw on RV64
whenever a 32-bit integer must be materialised and the Hi20 and Lo12
parts are non-zero. However, sometimes addi can be used equivalently
(whenever the sign extension behaviour of addiw would be a no-op). This
patch moves to using addiw only when necessary. Although there is
absolutely no advantage in terms of compressibility or performance, this
has the following advantages:
* It's more consistent with logic used elsewhere in the backend. For
instance, RISCVOptWInstrs will try to convert addiw to addi on the basis
it reduces test diffs vs RV32.
* This matches the lowering GCC does in its codegen path. Unlike LLVM,
GCC seems to have different expansion logic for the assembler vs
codegen. For codegen it will use lui+addi if possible, but expanding
`li` in the assembler will always produces lui+addiw as LLVM did prior
to this commit. As someone who has been looking at a lot of gcc vs clang
diffs lately, reducing unnecessary divergence is of at least some value.
* As the diff for fold-mem-offset.ll shows, we can fold memory offsets
in more cases when addi is used. Memory offset folding could be taught
to recognise when the addiw could be replaced with an addi, but that
seems unnecessary when we can simply change the logic in RISCVMatInt.

As pointed out by @topperc during review, making this change without
modifying RISCVOptWInstrs risks introducing some cases where we fail to
remove a sext.w that we removed before. I've incorporated a patch based
on a suggestion from Craig that avoids it, and also adds appropriate
RISCVOptWInstrs test cases.

The initial patch description noted that the main motivation was to
avoid unnecessary differences both for RV32/RV64 and when comparing GCC,
but noted that very occasionally we see a benefit from memory offset
folding kicking in when it didn't before. Looking at the dynamic
instruction count difference for SPEC benchmarks targeting rva22u64 and
it shows we actually get a meaningful
~4.3% reduction in dynamic icount for 519.lbm_r. Looking at the data
more closely, the codegen difference is in `LBM_performStreamCollideTRT`
which as a function accounts for ~98% for dynamically executed
instructions and the codegen diffs appear to be a knock-on effect of the
address merging reducing register pressure right from function entry
(for instance, we get a big reduction in dynamically executed loads in
that function).

Below is the icount data (rva22u64 -O3, no LTO):
```
Benchmark                Baseline            This PR   Diff (%)
============================================================
500.perlbench_r         174116601991    174115795810     -0.00%
502.gcc_r               218903280858    218903215788     -0.00%
505.mcf_r               131208029185    131207692803     -0.00%
508.namd_r              217497594322    217497594297     -0.00%
510.parest_r            289314486153    289313577652     -0.00%
511.povray_r             30640531048     30640765701      0.00%
519.lbm_r                95897914862     91712688050     -4.36%
520.omnetpp_r           134641549722    134867015683      0.17%
523.xalancbmk_r         281462762992    281432092673     -0.01%
525.x264_r              379776121941    379535558210     -0.06%
526.blender_r           659736022025    659738387343      0.00%
531.deepsjeng_r         349122867552    349122867481     -0.00%
538.imagick_r           238558760552    238558753269     -0.00%
541.leela_r             406578560612    406385135260     -0.05%
544.nab_r               400997131674    400996765827     -0.00%
557.xz_r                130079522194    129945515709     -0.10%

```

The instcounting setup I use doesn't have good support for drilling down
into functions from outside the linked executable (e.g. libc). The
difference in omnetpp all seems to come from there, and does not reflect
any degradation in codegen quality.

I can confirm with the current version of the PR there is no change in
the number of static sext.w across all the SPEC 2017 benchmarks
(rva22u64 O3)

Co-authored-by: Craig Topper <craig.topper@sifive.com>
2025-06-02 22:24:50 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBS
; RUN: llc -mtriple=riscv64 -mattr=+zbs,+zbb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBS
define signext i32 @bclr_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bclr_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
%neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a
ret i32 %and1
}
define signext i32 @bclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bclr_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a
ret i32 %and1
}
define signext i32 @bclr_i32_load(ptr %p, i32 signext %b) nounwind {
; RV64I-LABEL: bclr_i32_load:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, ptr %p
%shl = shl i32 1, %b
%neg = xor i32 %shl, -1
%and1 = and i32 %neg, %a
ret i32 %and1
}
define i64 @bclr_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bclr_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: ret
%and = and i64 %b, 63
%shl = shl nuw i64 1, %and
%neg = xor i64 %shl, -1
%and1 = and i64 %neg, %a
ret i64 %and1
}
define i64 @bclr_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bclr_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclr_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclr a0, a0, a1
; RV64ZBS-NEXT: ret
%shl = shl i64 1, %b
%neg = xor i64 %shl, -1
%and1 = and i64 %neg, %a
ret i64 %and1
}
define signext i32 @bset_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bset_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
%or = or i32 %shl, %a
ret i32 %or
}
define signext i32 @bset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bset_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%or = or i32 %shl, %a
ret i32 %or
}
define signext i32 @bset_i32_load(ptr %p, i32 signext %b) nounwind {
; RV64I-LABEL: bset_i32_load:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, ptr %p
%shl = shl i32 1, %b
%or = or i32 %shl, %a
ret i32 %or
}
; We can use bsetw for 1 << x by setting the first source to zero.
define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
; RV64I-LABEL: bset_i32_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i32_zero:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %a
ret i32 %shl
}
define i64 @bset_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bset_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63
%shl = shl nuw i64 1, %conv
%or = or i64 %shl, %a
ret i64 %or
}
define i64 @bset_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bset_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, a0, a1
; RV64ZBS-NEXT: ret
%shl = shl i64 1, %b
%or = or i64 %shl, %a
ret i64 %or
}
; We can use bsetw for 1 << x by setting the first source to zero.
define signext i64 @bset_i64_zero(i64 signext %a) nounwind {
; RV64I-LABEL: bset_i64_zero:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: sll a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_i64_zero:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: ret
%shl = shl i64 1, %a
ret i64 %shl
}
define signext i32 @binv_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: binv_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shl = shl nuw i32 1, %and
%xor = xor i32 %shl, %a
ret i32 %xor
}
define signext i32 @binv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: binv_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%shl = shl i32 1, %b
%xor = xor i32 %shl, %a
ret i32 %xor
}
define signext i32 @binv_i32_load(ptr %p, i32 signext %b) nounwind {
; RV64I-LABEL: binv_i32_load:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a0, 0(a0)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i32_load:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: lw a0, 0(a0)
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
%a = load i32, ptr %p
%shl = shl i32 1, %b
%xor = xor i32 %shl, %a
ret i32 %xor
}
define i64 @binv_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: binv_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63
%shl = shl nuw i64 1, %conv
%xor = xor i64 %shl, %a
ret i64 %xor
}
define i64 @binv_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: binv_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sll a1, a2, a1
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binv_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binv a0, a0, a1
; RV64ZBS-NEXT: ret
%shl = shl nuw i64 1, %b
%xor = xor i64 %shl, %a
ret i64 %xor
}
define signext i32 @bext_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bext_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a1, a1, 31
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%and = and i32 %b, 31
%shr = lshr i32 %a, %and
%and1 = and i32 %shr, 1
ret i32 %and1
}
define signext i32 @bext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: bext_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, %b
%and1 = and i32 %shr, 1
ret i32 %and1
}
; This gets previous converted to (i1 (truncate (srl X, Y)). Make sure we are
; able to use bext.
define void @bext_i32_trunc(i32 signext %0, i32 signext %1) {
; RV64I-LABEL: bext_i32_trunc:
; RV64I: # %bb.0:
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: beqz a0, .LBB19_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB19_2:
; RV64I-NEXT: tail bar
;
; RV64ZBS-LABEL: bext_i32_trunc:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: beqz a0, .LBB19_2
; RV64ZBS-NEXT: # %bb.1:
; RV64ZBS-NEXT: ret
; RV64ZBS-NEXT: .LBB19_2:
; RV64ZBS-NEXT: tail bar
%3 = shl i32 1, %1
%4 = and i32 %3, %0
%5 = icmp eq i32 %4, 0
br i1 %5, label %6, label %7
6: ; preds = %2
tail call void @bar()
br label %7
7: ; preds = %6, %2
ret void
}
declare void @bar()
define i64 @bext_i64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bext_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%conv = and i64 %b, 63
%shr = lshr i64 %a, %conv
%and1 = and i64 %shr, 1
ret i64 %and1
}
define i64 @bext_i64_no_mask(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: bext_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
; RV64I-NEXT: andi a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bext_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bext a0, a0, a1
; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, %b
%and1 = and i64 %shr, 1
ret i64 %and1
}
define signext i32 @bexti_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bexti_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i32:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%shr = lshr i32 %a, 5
%and = and i32 %shr, 1
ret i32 %and
}
define i64 @bexti_i64(i64 %a) nounwind {
; RV64I-LABEL: bexti_i64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%shr = lshr i64 %a, 5
%and = and i64 %shr, 1
ret i64 %and
}
define signext i32 @bexti_i32_cmp(i32 signext %a) nounwind {
; RV64I-LABEL: bexti_i32_cmp:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i32_cmp:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%and = and i32 %a, 32
%cmp = icmp ne i32 %and, 0
%zext = zext i1 %cmp to i32
ret i32 %zext
}
define i64 @bexti_i64_cmp(i64 %a) nounwind {
; RV64I-LABEL: bexti_i64_cmp:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 58
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bexti_i64_cmp:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bexti a0, a0, 5
; RV64ZBS-NEXT: ret
%and = and i64 %a, 32
%cmp = icmp ne i64 %and, 0
%zext = zext i1 %cmp to i64
ret i64 %zext
}
define signext i32 @bclri_i32_10(i32 signext %a) nounwind {
; CHECK-LABEL: bclri_i32_10:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, -1025
; CHECK-NEXT: ret
%and = and i32 %a, -1025
ret i32 %and
}
define signext i32 @bclri_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: bclri_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64ZBS-NEXT: ret
%and = and i32 %a, -2049
ret i32 %and
}
define signext i32 @bclri_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: bclri_i32_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64ZBS-NEXT: ret
%and = and i32 %a, -1073741825
ret i32 %and
}
define signext i32 @bclri_i32_31(i32 signext %a) nounwind {
; CHECK-LABEL: bclri_i32_31:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a0, a0, 33
; CHECK-NEXT: srli a0, a0, 33
; CHECK-NEXT: ret
%and = and i32 %a, -2147483649
ret i32 %and
}
define i64 @bclri_i64_10(i64 %a) nounwind {
; CHECK-LABEL: bclri_i64_10:
; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, -1025
; CHECK-NEXT: ret
%and = and i64 %a, -1025
ret i64 %and
}
define i64 @bclri_i64_11(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_11:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addi a1, a1, 2047
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 11
; RV64ZBS-NEXT: ret
%and = and i64 %a, -2049
ret i64 %and
}
define i64 @bclri_i64_30(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 786432
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 30
; RV64ZBS-NEXT: ret
%and = and i64 %a, -1073741825
ret i64 %and
}
define i64 @bclri_i64_31(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_31:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 31
; RV64ZBS-NEXT: ret
%and = and i64 %a, -2147483649
ret i64 %and
}
define i64 @bclri_i64_62(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_62:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 62
; RV64ZBS-NEXT: ret
%and = and i64 %a, -4611686018427387905
ret i64 %and
}
define i64 @bclri_i64_63(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_63:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 63
; RV64ZBS-NEXT: ret
%and = and i64 %a, -9223372036854775809
ret i64 %and
}
define i64 @bclri_i64_large0(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_large0:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044480
; RV64I-NEXT: addi a1, a1, -256
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_large0:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, -256
; RV64ZBS-NEXT: bclri a0, a0, 24
; RV64ZBS-NEXT: ret
%and = and i64 %a, -16777472
ret i64 %and
}
define i64 @bclri_i64_large1(i64 %a) nounwind {
; RV64I-LABEL: bclri_i64_large1:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1044464
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bclri_i64_large1:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bclri a0, a0, 16
; RV64ZBS-NEXT: bclri a0, a0, 24
; RV64ZBS-NEXT: ret
%and = and i64 %a, -16842753
ret i64 %and
}
define signext i32 @bseti_i32_10(i32 signext %a) nounwind {
; CHECK-LABEL: bseti_i32_10:
; CHECK: # %bb.0:
; CHECK-NEXT: ori a0, a0, 1024
; CHECK-NEXT: ret
%or = or i32 %a, 1024
ret i32 %or
}
define signext i32 @bseti_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: bseti_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 11
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64ZBS-NEXT: ret
%or = or i32 %a, 2048
ret i32 %or
}
define signext i32 @bseti_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: bseti_i32_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64ZBS-NEXT: ret
%or = or i32 %a, 1073741824
ret i32 %or
}
define signext i32 @bseti_i32_31(i32 signext %a) nounwind {
; CHECK-LABEL: bseti_i32_31:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ret
%or = or i32 %a, 2147483648
ret i32 %or
}
define i64 @bseti_i64_10(i64 %a) nounwind {
; CHECK-LABEL: bseti_i64_10:
; CHECK: # %bb.0:
; CHECK-NEXT: ori a0, a0, 1024
; CHECK-NEXT: ret
%or = or i64 %a, 1024
ret i64 %or
}
define i64 @bseti_i64_11(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_11:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 11
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 11
; RV64ZBS-NEXT: ret
%or = or i64 %a, 2048
ret i64 %or
}
define i64 @bseti_i64_30(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 30
; RV64ZBS-NEXT: ret
%or = or i64 %a, 1073741824
ret i64 %or
}
define i64 @bseti_i64_31(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_31:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 31
; RV64ZBS-NEXT: ret
%or = or i64 %a, 2147483648
ret i64 %or
}
define i64 @bseti_i64_62(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_62:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 62
; RV64ZBS-NEXT: ret
%or = or i64 %a, 4611686018427387904
ret i64 %or
}
define i64 @bseti_i64_63(i64 %a) nounwind {
; RV64I-LABEL: bseti_i64_63:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bseti_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 63
; RV64ZBS-NEXT: ret
%or = or i64 %a, 9223372036854775808
ret i64 %or
}
define signext i32 @binvi_i32_10(i32 signext %a) nounwind {
; CHECK-LABEL: binvi_i32_10:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, 1024
; CHECK-NEXT: ret
%xor = xor i32 %a, 1024
ret i32 %xor
}
define signext i32 @binvi_i32_11(i32 signext %a) nounwind {
; RV64I-LABEL: binvi_i32_11:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 11
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i32_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 2048
ret i32 %xor
}
define signext i32 @binvi_i32_30(i32 signext %a) nounwind {
; RV64I-LABEL: binvi_i32_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i32_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64ZBS-NEXT: ret
%xor = xor i32 %a, 1073741824
ret i32 %xor
}
define signext i32 @binvi_i32_31(i32 signext %a) nounwind {
; CHECK-LABEL: binvi_i32_31:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: ret
%xor = xor i32 %a, 2147483648
ret i32 %xor
}
define i64 @binvi_i64_10(i64 %a) nounwind {
; CHECK-LABEL: binvi_i64_10:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, 1024
; CHECK-NEXT: ret
%xor = xor i64 %a, 1024
ret i64 %xor
}
define i64 @binvi_i64_11(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_11:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 11
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_11:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 11
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 2048
ret i64 %xor
}
define i64 @binvi_i64_30(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_30:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 262144
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_30:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 30
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 1073741824
ret i64 %xor
}
define i64 @binvi_i64_31(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_31:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 31
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_31:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 31
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 2147483648
ret i64 %xor
}
define i64 @binvi_i64_62(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_62:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_62:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 62
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4611686018427387904
ret i64 %xor
}
define i64 @binvi_i64_63(i64 %a) nounwind {
; RV64I-LABEL: binvi_i64_63:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: binvi_i64_63:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 63
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 9223372036854775808
ret i64 %xor
}
define i64 @xor_i64_large(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_large:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_large:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 0
; RV64ZBS-NEXT: binvi a0, a0, 32
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4294967297
ret i64 %xor
}
define i64 @xor_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addi a1, a1, 3
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_4099:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 3
; RV64ZBS-NEXT: binvi a0, a0, 12
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 4099
ret i64 %xor
}
define i64 @xor_i64_96(i64 %a) nounwind {
; CHECK-LABEL: xor_i64_96:
; CHECK: # %bb.0:
; CHECK-NEXT: xori a0, a0, 96
; CHECK-NEXT: ret
%xor = xor i64 %a, 96
ret i64 %xor
}
define i64 @or_i64_large(i64 %a) nounwind {
; RV64I-LABEL: or_i64_large:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_large:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bseti a0, a0, 0
; RV64ZBS-NEXT: bseti a0, a0, 32
; RV64ZBS-NEXT: ret
%or = or i64 %a, 4294967297
ret i64 %or
}
define i64 @xor_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: xor_i64_66901:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: xor_i64_66901:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: xori a0, a0, 1365
; RV64ZBS-NEXT: binvi a0, a0, 16
; RV64ZBS-NEXT: ret
%xor = xor i64 %a, 66901
ret i64 %xor
}
define i64 @or_i64_4099(i64 %a) nounwind {
; RV64I-LABEL: or_i64_4099:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addi a1, a1, 3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_4099:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 3
; RV64ZBS-NEXT: bseti a0, a0, 12
; RV64ZBS-NEXT: ret
%or = or i64 %a, 4099
ret i64 %or
}
define i64 @or_i64_96(i64 %a) nounwind {
; CHECK-LABEL: or_i64_96:
; CHECK: # %bb.0:
; CHECK-NEXT: ori a0, a0, 96
; CHECK-NEXT: ret
%or = or i64 %a, 96
ret i64 %or
}
define i64 @or_i64_66901(i64 %a) nounwind {
; RV64I-LABEL: or_i64_66901:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addi a1, a1, 1365
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: or_i64_66901:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: ori a0, a0, 1365
; RV64ZBS-NEXT: bseti a0, a0, 16
; RV64ZBS-NEXT: ret
%or = or i64 %a, 66901
ret i64 %or
}
define signext i32 @bset_trailing_ones_i32_mask(i32 signext %a) nounwind {
; RV64I-LABEL: bset_trailing_ones_i32_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_trailing_ones_i32_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: andi a0, a0, 31
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: addi a0, a0, -1
; RV64ZBS-NEXT: ret
%and = and i32 %a, 31
%shift = shl nsw i32 -1, %and
%not = xor i32 %shift, -1
ret i32 %not
}
define signext i32 @bset_trailing_ones_i32_no_mask(i32 signext %a) nounwind {
; RV64I-LABEL: bset_trailing_ones_i32_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_trailing_ones_i32_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: addiw a0, a0, -1
; RV64ZBS-NEXT: ret
%shift = shl nsw i32 -1, %a
%not = xor i32 %shift, -1
ret i32 %not
}
define signext i64 @bset_trailing_ones_i64_mask(i64 signext %a) nounwind {
; RV64I-LABEL: bset_trailing_ones_i64_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: sll a0, a1, a0
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_trailing_ones_i64_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: addi a0, a0, -1
; RV64ZBS-NEXT: ret
%and = and i64 %a, 63
%shift = shl nsw i64 -1, %and
%not = xor i64 %shift, -1
ret i64 %not
}
define signext i64 @bset_trailing_ones_i64_no_mask(i64 signext %a) nounwind {
; RV64I-LABEL: bset_trailing_ones_i64_no_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: sll a0, a1, a0
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: bset_trailing_ones_i64_no_mask:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: addi a0, a0, -1
; RV64ZBS-NEXT: ret
%shift = shl nsw i64 -1, %a
%not = xor i64 %shift, -1
ret i64 %not
}
define i1 @icmp_eq_pow2(i32 signext %x) nounwind {
; RV64I-LABEL: icmp_eq_pow2:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 8
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: icmp_eq_pow2:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 15
; RV64ZBS-NEXT: seqz a0, a0
; RV64ZBS-NEXT: ret
%cmp = icmp eq i32 %x, 32768
ret i1 %cmp
}
define i1 @icmp_eq_pow2_64(i64 %x) nounwind {
; RV64I-LABEL: icmp_eq_pow2_64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 40
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: icmp_eq_pow2_64:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 40
; RV64ZBS-NEXT: seqz a0, a0
; RV64ZBS-NEXT: ret
%cmp = icmp eq i64 %x, 1099511627776
ret i1 %cmp
}
define i1 @icmp_ne_pow2(i32 signext %x) nounwind {
; RV64I-LABEL: icmp_ne_pow2:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 8
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: icmp_ne_pow2:
; RV64ZBS: # %bb.0:
; RV64ZBS-NEXT: binvi a0, a0, 15
; RV64ZBS-NEXT: seqz a0, a0
; RV64ZBS-NEXT: ret
%cmp = icmp eq i32 %x, 32768
ret i1 %cmp
}
define i1 @icmp_eq_nonpow2(i32 signext %x) nounwind {
; CHECK-LABEL: icmp_eq_nonpow2:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: seqz a0, a0
; CHECK-NEXT: ret
%cmp = icmp eq i32 %x, 32767
ret i1 %cmp
}
define signext i32 @fold_sextinreg_shl_to_sllw(i64 %x) nounwind {
; CHECK-LABEL: fold_sextinreg_shl_to_sllw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: sllw a0, a1, a0
; CHECK-NEXT: ret
entry:
%mask = and i64 %x, 31
%shl = shl i64 1, %mask
%trunc = trunc i64 %shl to i32
ret i32 %trunc
}
define signext i32 @fold_sextinreg_shl_to_sllw_large_shamt(i64 %x) nounwind {
; RV64I-LABEL: fold_sextinreg_shl_to_sllw_large_shamt:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: sll a0, a1, a0
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ret
;
; RV64ZBS-LABEL: fold_sextinreg_shl_to_sllw_large_shamt:
; RV64ZBS: # %bb.0: # %entry
; RV64ZBS-NEXT: bset a0, zero, a0
; RV64ZBS-NEXT: sext.w a0, a0
; RV64ZBS-NEXT: ret
entry:
%mask = and i64 %x, 63
%shl = shl i64 1, %mask
%trunc = trunc i64 %shl to i32
ret i32 %trunc
}
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