e6bf48d110
As of rev ea222be0d, LLVMs assembler will actually try to honour the "fill value" part of p2align directives. X86 printed these as 0x90, which isn't actually what it wanted: we want multi-byte nops for .text padding. Compiling via a textual assembly file produces single-byte nop padding since ea222be0d but the built-in assembler will produce multi-byte nops. This divergent behaviour is undesirable. To fix: don't set the byte padding field for x86, which allows the assembler to pick multi-byte nops. Test that we get the same multi-byte padding when compiled via textual assembly or directly to object file. Added same-align-bytes-with-llasm-llobj.ll to that effect, updated numerous other tests to not contain check-lines for the explicit padding.
31 lines
1.0 KiB
LLVM
31 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mcpu=i386 | FileCheck %s
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define i32 @foo(i32 %t, i32 %C) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: # %cond_true
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: cmpl $40, %ecx
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; CHECK-NEXT: jl .LBB0_1
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; CHECK-NEXT: # %bb.2: # %bb12
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; CHECK-NEXT: retl
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entry:
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br label %cond_true
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cond_true: ; preds = %cond_true, %entry
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%t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=2]
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%tmp7 = add i32 %t_addr.0.0, 1 ; <i32> [#uses=1]
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%tmp = icmp sgt i32 %C, 39 ; <i1> [#uses=1]
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br i1 %tmp, label %bb12, label %cond_true
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bb12: ; preds = %cond_true
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ret i32 %t_addr.0.0
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}
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