e6bf48d110
As of rev ea222be0d, LLVMs assembler will actually try to honour the "fill value" part of p2align directives. X86 printed these as 0x90, which isn't actually what it wanted: we want multi-byte nops for .text padding. Compiling via a textual assembly file produces single-byte nop padding since ea222be0d but the built-in assembler will produce multi-byte nops. This divergent behaviour is undesirable. To fix: don't set the byte padding field for x86, which allows the assembler to pick multi-byte nops. Test that we get the same multi-byte padding when compiled via textual assembly or directly to object file. Added same-align-bytes-with-llasm-llobj.ll to that effect, updated numerous other tests to not contain check-lines for the explicit padding.
79 lines
2.8 KiB
LLVM
79 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=x86_64-unknown-freebsd15.0 < %s | FileCheck %s
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%struct.anon.5.28.78.99.149.119 = type { [4 x i8] }
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@vga_load_state_p = external dso_local global ptr, align 8
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@vga_load_state_data = external dso_local global i8, align 1
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define dso_local void @vga_load_state() #0 {
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; CHECK-LABEL: vga_load_state:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: jg .LBB0_3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: jle .LBB0_2
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; CHECK-NEXT: .LBB0_3: # %for.end
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; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_4: # %for.cond1
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: movq vga_load_state_p(%rip), %rax
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; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
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; CHECK-NEXT: movzbl (%rax,%rcx), %eax
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; CHECK-NEXT: movb %al, vga_load_state_data(%rip)
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; CHECK-NEXT: leal 1(%rcx), %eax
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; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: jmp .LBB0_4
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entry:
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%i = alloca i32, align 4
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store i32 0, ptr %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.body, %entry
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%i1 = load i32, ptr %i, align 4
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%cmp = icmp slt i32 %i1, 4
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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call void asm sideeffect "", "{ax},~{dirflag},~{fpsr},~{flags}"(i8 0) #1
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%i2 = load i32, ptr %i, align 4
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%inc = add nsw i32 %i2, 1
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store i32 %inc, ptr %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond
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store i32 0, ptr %i, align 4
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br label %for.cond1
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for.cond1: ; preds = %for.cond1, %for.end
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call void asm sideeffect "", "N{dx},~{dirflag},~{fpsr},~{flags}"(i32 poison) #1
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%i3 = load ptr, ptr @vga_load_state_p, align 8
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%regs = getelementptr inbounds %struct.anon.5.28.78.99.149.119, ptr %i3, i32 0, i32 0
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%i4 = load i32, ptr %i, align 4
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%idxprom = sext i32 %i4 to i64
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%arrayidx = getelementptr inbounds [4 x i8], ptr %regs, i64 0, i64 %idxprom
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%i5 = load i8, ptr %arrayidx, align 1
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store i8 %i5, ptr @vga_load_state_data, align 1
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%i6 = load i32, ptr %i, align 4
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%inc5 = add nsw i32 %i6, 1
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store i32 %inc5, ptr %i, align 4
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br label %for.cond1, !llvm.loop !0
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}
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attributes #0 = { "tune-cpu"="generic" }
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attributes #1 = { nounwind }
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!0 = distinct !{!0, !1}
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!1 = !{!"llvm.loop.mustprogress"}
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