dc90af501f
New versions I2.1, F2.2, D2.2 A2.1 Make F and Zfinx imply Zicsr. Make G imply Zifencei. This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly. See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D147179
22 lines
849 B
ArmAsm
22 lines
849 B
ArmAsm
## When a user specifies an architecture extension which conflicts with an
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## architecture attribute, we use the architecture attribute instead of the
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## command line option.
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##
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## This test uses option '-mattr=+e' to specify the "e" extension. However,
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## there is an architecture attribute in the file to specify rv32i. We will
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## use rv32i to assemble the file instead of rv32e.
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+e -filetype=obj -o - \
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# RUN: | llvm-readobj -A - | FileCheck %s
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.attribute arch, "rv32i2p1"
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## Invalid operand for RV32E, because x16 is an invalid register for RV32E.
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## Use RV32I to assemble, since it will not trigger an assembly error.
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lui x16, 1
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## Check that the architecture attribute is not overridden by the command line
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## option.
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# CHECK: Tag: 5
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# CHECK-NEXT: TagName: arch
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# CHECK-NEXT: Value: rv32i2p1
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