f109517d15
Add the ability to override the disassembly CPU and CPU features through a target setting (`target.disassembly-cpu` and `target.disassembly-features`) and a `disassemble` command option (`--cpu` and `--features`). This is especially relevant for architectures like RISC-V which relies heavily on CPU extensions. The majority of this patch is plumbing the options through. I recommend looking at DisassemblerLLVMC and the test for the observable change in behavior.
83 lines
2.5 KiB
C++
83 lines
2.5 KiB
C++
//===-- TestArm64Disassembly.cpp ------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "gtest/gtest.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/Disassembler.h"
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#include "lldb/Utility/ArchSpec.h"
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#include "lldb/Target/ExecutionContext.h"
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#include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
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#include "llvm/Support/TargetSelect.h"
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using namespace lldb;
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using namespace lldb_private;
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namespace {
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class TestArm64Disassembly : public testing::Test {
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public:
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static void SetUpTestCase();
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static void TearDownTestCase();
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// virtual void SetUp() override { }
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// virtual void TearDown() override { }
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protected:
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};
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void TestArm64Disassembly::SetUpTestCase() {
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llvm::InitializeAllTargets();
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llvm::InitializeAllAsmPrinters();
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llvm::InitializeAllTargetMCs();
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llvm::InitializeAllDisassemblers();
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DisassemblerLLVMC::Initialize();
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}
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void TestArm64Disassembly::TearDownTestCase() {
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DisassemblerLLVMC::Terminate();
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}
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} // namespace
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TEST_F(TestArm64Disassembly, TestArmv81Instruction) {
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ArchSpec arch("arm64-apple-ios");
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const unsigned num_of_instructions = 2;
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uint8_t data[] = {
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0xff, 0x43, 0x00, 0xd1, // 0xd10043ff : sub sp, sp, #0x10
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0x62, 0x7c, 0xa1, 0xc8, // 0xc8a17c62 : cas x1, x2, [x3] (cas defined in ARM v8.1 & newer)
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};
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DisassemblerSP disass_sp;
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Address start_addr(0x100);
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disass_sp = Disassembler::DisassembleBytes(
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arch, nullptr, nullptr, nullptr, nullptr, start_addr, &data, sizeof(data),
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num_of_instructions, false);
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// If we failed to get a disassembler, we can assume it is because
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// the llvm we linked against was not built with the ARM target,
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// and we should skip these tests without marking anything as failing.
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if (disass_sp) {
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const InstructionList inst_list (disass_sp->GetInstructionList());
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EXPECT_EQ (num_of_instructions, inst_list.GetSize());
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InstructionSP inst_sp;
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const char *mnemonic;
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ExecutionContext exe_ctx (nullptr, nullptr, nullptr);
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inst_sp = inst_list.GetInstructionAtIndex (0);
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mnemonic = inst_sp->GetMnemonic(&exe_ctx);
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ASSERT_STREQ ("sub", mnemonic);
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inst_sp = inst_list.GetInstructionAtIndex (1);
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mnemonic = inst_sp->GetMnemonic(&exe_ctx);
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ASSERT_STREQ ("cas", mnemonic);
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}
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}
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