9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
40 lines
1.6 KiB
LLVM
40 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-FMF,GCN-SAFE %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; Test that the -enable-no-signed-zeros-fp-math flag works
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; GCN-LABEL: {{^}}fneg_fsub_f32_fmf:
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; GCN: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; GCN-FMF-NOT: xor
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define amdgpu_kernel void @fneg_fsub_f32_fmf(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%add = add i32 %tid, 1
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%gep = getelementptr float, ptr addrspace(1) %in, i32 %tid
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%b_ptr = getelementptr float, ptr addrspace(1) %in, i32 %add
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%a = load float, ptr addrspace(1) %gep, align 4
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%b = load float, ptr addrspace(1) %b_ptr, align 4
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%result = fsub fast float %a, %b
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%neg.result = fsub fast float -0.0, %result
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store float %neg.result, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fsub_f32_safe:
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; GCN: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}
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; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]]
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define amdgpu_kernel void @fneg_fsub_f32_safe(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%add = add i32 %tid, 1
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%gep = getelementptr float, ptr addrspace(1) %in, i32 %tid
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%b_ptr = getelementptr float, ptr addrspace(1) %in, i32 %add
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%a = load float, ptr addrspace(1) %gep, align 4
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%b = load float, ptr addrspace(1) %b_ptr, align 4
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%result = fsub float %a, %b
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%neg.result = fsub float -0.0, %result
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store float %neg.result, ptr addrspace(1) %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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